The SLG46535 provides a small, low power component for commonly used mixed- signal functions. The user creates their circuit design by programming the one time Non- Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46535. This highly versatile device allows a wide variety of mixed- signal functions to be designed within a very small, low power single integrated circuit.
The additional power supply (VDD2) on the SLG46535 provides the ability to interface two independent voltage domains within the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically by internal logic) to both VDD and VDD2 voltage domains. Using the available macrocells designers can implement mixed- signal functions bridging both domains or simply pass through level- translation in both High to Low and Low to High directions.
The macrocells in the device include the following:
Three Analog Comparators (ACMP) Nineteen Combination Function Macrocells Three Selectable DFF/Latch or 2- bit LUTs One Selectable Continuous DFF/Latch or 3- bit LUT Four Selectable DFF/Latch or 3- bit LUTs One Selectable Pipe Delay or 3- bit LUT One Selectable Programmable Function Generator or 2- bit LUT Five 8- bit delays/counters or 3- bit LUTs Two 16- bit delays/counters or 4- bit LUTs Two Deglitch Filters with Edge Detectors Asynchronous State Machine Eight States Flexible input logic from state transitions Serial Communications I²C Protocol compliant Pipe Delay - 16 stage/3 output (Part of Combination Function Macrocell) Programmable Delay Additional Logic Function One Inverter Two Oscillators (OSC) Configurable 25 kHz/2 MHz 25 MHz RC Oscillator Crystal Oscillator Power- On- Reset (POR) Eight Byte RAM + OTP User Memory RAM Memory space that is readable and writable via I²C User defined initial values transferred from OTP
RENESAS SLG46535V