MICROCHIP USB5533B-5000JZXTR

The USB5533B hub is a 3-port SuperSpeed/Hi-Speed, low-power, configurable hub controller family fully compliant with the USB 3.0 Specification. The USB5533B supports 5 Gbps SuperSpeed (SS), 480 Mbps HiSpeed (HS), 12 Mbps Full-Speed (FS) and 1.5 Mbps Low-Speed (LS) USB signaling for complete coverage of all defined USB operating speeds. The USB5533B supports USB 2.0 speeds through its USB 2.0 hub controller. The new SuperSpeed hub controller operates in parallel with the USB 2.0 controller, so the 5 Gbps SuperSpeed data transfers are not affected by the slower USB 2.0 traffic. The USB5533B supports battery charging on a per port basis. On battery charging enabled ports, the devices provide automatic USB data line handshaking. The handshaking supports USB 1.2 Charging Downstream Port (CDP), Dedicated Charging Port (DCP) and nonUSB 1.2 devices. The USB5533B is configured for operation through internal default settings, where custom configurations are supported through an on-chip OTP ROM, an external SPI ROM, or SMBus.

• USB 3.0 compliant 5 Gbps, 480 Mbps, 12 Mbps and 1.5 Mbps operation, USB pins are 5 V tolerant - Integrated termination and pull-up/pull-down resistors
• Three downstream USB 3.0 ports
• Supports battery charging of most popular battery powered devices - USB-IF Battery Charging rev. 1.2 support (DCP & CDP) Apple Portable product charger emulation - Blackberry charger emulation - Chinese YD/T 1591-2006 charger emulation - Chinese YD/T 1591-2009 charger emulation - Supports additional portable devices
• Emulates portable/handheld native wall chargers - Charging profiles emulate a handheld device’s wall charger to enable fast charging (minutes vs. hours)
• Enables charging from a mobile platform that is off
• Support tablets’ high current requirements
• Optimized for low-power operation and low thermal dissipation
• Vendor Specific Messaging (VSM) support for firmware upload over USB
• Configuration via OTP ROM, SPI ROM, or SMBus
• On-chip 8051 μc manages VBUS, and other hub signals
• 8 KB RAM, 32 KB ROM
• One Time programmable (OTP) ROM: 8 kbit - Includes on-chip charge pump
• Single 25 MHz XTAL or clock input for all on-chip PLL and clocking requirements
• Supports JTAG boundary scan
• PHYBoost (USB 2.0) - Selectable drive strength for improved signal integrity
• VariSense (USB 2.0) - controls the receiver sensitivity enabling four programmable levels of USB signal receive sensitivity
• IETF RFC 4122 compliant 128-bit UUID