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MICROCHIP 23K256-E/SN product image
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MICROCHIP 23K256-E/SNRoHS

Manufacturer
MPN
23K256-E/SN
LCSC Part #
C615092
Packaging
SOIC-8
Customer #
Key Attributes
256-Kbit SPI Bus Serial SRAM
Datasheetpdf iconMICROCHIP 23K256-E/SN
In-Stock: 100
100 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 3.0462$ 3.05
10+$ 2.6071$ 26.07
30+$ 2.3464$ 70.39
100+$ 2.0825$ 208.25
500+$ 1.96$ 980.00
1,000+$ 1.9056$ 1905.60
Standard Packaging100/Full Tube
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory (ICs)
ManufacturerMICROCHIP
PackagingSOIC-8
Memory Size256Kbit
Voltage - Supply2.7V~3.6V
Operating temperature-40℃~+125℃
Access Time-
FeaturesAuto power-down function
Current - Supply10mA
Standby Supply Current4uA
InterfaceSPI

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging100
Sales UnitPiece

Introduction

AI Translation

The 23X256 are 256-Kbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin. While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 23X256 is a 32,768-byte Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 23X256 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 23X256 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. The 23A256/23K256 has three modes of operation that are selected by setting bits 7 and 6 in the STATUS register. The modes of operation are Byte, Page and Burst. The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23X256 followed by the 16-bit address, with the first MSb of the address being a “don’t care” bit. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin.

Features

AI Translation
  • Maximum Clock 20 MHz
  • Low-Power CMOS Technology:
    • Read Current: 3 mA at 1 MHz
    • Standby Current: 4 μA maximum at +85℃
  • 32,768x8 -bit Organization
  • 32-Byte Page
  • HOLD Pin
  • Flexible Operating Modes:
    • Byte read and write
    • Page mode (32-Byte Page)
    • Sequential mode
  • Sequential Read/Write
  • High Reliability
  • Temperature Ranges Supported:
    • Industrial (I): -40℃ to +85℃
    • Extended (E): -40℃ to +125℃
  • Pb-Free and RoHS Compliant, Halogen Free
  • Automotive AEC-Q100 Qualified