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TI AM6254ATCGGAALWRoHS

Manufacturer
TI
MPN
AM6254ATCGGAALW
LCSC Part #
C6120421
Packaging
FCCSP-425(13x13)
Customer #
Key Attributes
Performance of Sitara processors in terms of memory, multimedia, functional safety, high-speed interfaces, etc.
Datasheetpdf iconTI AM6254ATCGGAALW

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microprocessors
ManufacturerTI
PackagingFCCSP-425(13x13)
CPU CoreARM Cortex-ASeries
CPU Maximum Speed1.4GHz
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging119
Sales UnitPiece

Features

AI Translation
  • Processor Cores:
    • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4 GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 ICache with SECDED ECC and 32KB L1 ICache with Parity protection
    • Single-core Arm Cortex-M4F MCU at up to 400 MHz
    • 256KB SRAM with SECDED ECC
    • Dedicated Device/Power Manager
  • Multimedia:
    • Display subsystem:
      • Dual display support
      • 1920x1080 @ 60fps for each display
      • 1x 2048x1080 + 1x 1280x720
      • Up to 165 MHz pixel clock support with Independent PLL for each display
      • OLDI (4 lanes LVDS - 2x) and DPI (24-bit RGB LVCMOS)
      • Support safety feature such as freeze frame detection and MISR data check
    • 3D Graphics Processing Unit:
      • 1 pixel per clock or higher
      • Fillrate greater than 500 Mpixels/sec

      • 500 MTexels/s, >8 GFLOPs

      • Supports at least 2 composition layers
      • Supports up to 2048x1080 @60fps
      • Supports ARGB32, RGB565 and YUV formats
      • 2D graphics capable
      • OpenGL ES 3.1, Vulkan 1.2
    • One Camera Serial interface (CSI-Rx):
      • 4 Lane with DPHY
      • MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
      • Support for 1,2,3 or 4 data lane mode up to 1.5Gbps
      • ECC verification/correction with CRC check + ECC on RAM
      • Virtual Channel support (up to 16)
      • Ability to write stream data directly to DDR via DMA
  • Memory Subsystem:
    • Up to 816KB of On-chip RAM
    • 64KB of On-chip RAM (OCSRAM) with SECDED ECC, Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
    • DDR Subsystem (DDRSS):
      • Supports LPDDR4, DDR4 memory types
      • 16-Bit data bus with inline ECC
      • Supports speeds up to 1600 MT/s
      • Max addressable range: 8GBytes with DDR4, 4GBytes with LPDDR4
  • Functional Safety:
    • Compliant targeted [Industrial]
      • Developed for functional safety applications
      • Documentation will be available to aid IEC 61508 functional safety system design
      • Systematic capability up to SIL 3 targeted
      • Hardware Integrity up to SIL 2 targeted
      • Safety-related certification: IEC 61508 by TUV SUD planned
    • Compliant targeted [Automotive]
      • Developed for functional safety applications
      • Documentation will be available to aid ISO 26262 functional safety system design
      • Systematic capability up to ASIL D targeted
      • Hardware integrity up to ASIL B targeted
      • Safety-related certification: ISO 26262 by TUV SUD planned
    • AEC - Q100 qualified
  • Security:
    • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
    • Trusted Execution Environment (TEE) supported
      • Arm TrustZone based TEE
      • Extensive firewall support for isolation
      • Secure watchdog/timer/IPC
      • Secure storage support
      • Replay Protected Memory Block (RPMB) support
    • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
    • Cryptographic acceleration supported
      • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
        • AES - 128-/192-/256-Bit key sizes
        • SHA2 - 224-/256-/384-/512-Bit key sizes
        • DRBG with true random number generator
        • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
    • Debugging security
      • Secure software controlled debug access
      • Security aware debugging
  • PRU Subsystem:
    • Dual-core Programmable Real-Time Unit Subsystem (PRUSS) running up to 333 MHz
    • Intended for driving GPIO for cycle accurate protocols such as additional:
      • General Purpose Input/Output (GPIO)
      • UARTs
      • I2C
      • External ADC
    • 16KByte program memory per PRU with SECDED ECC
    • 8KB data memory per PRU with SECDED ECC
    • 32KB general purpose memory with SECDED ECC
    • CRC32/16 HW accelerator
    • Scratch PAD memory with 3 banks of 30x32-bit registers
    • 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
    • 1 interrupt controller (INTC), minimum of 64 input events supported
  • High-Speed Interfaces:
    • Integrated Ethernet switch supporting (total 2 external ports)
      • RMII(10/100) or RGMII (10/100/1000)
      • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
      • Clause 45 MDIO PHY management
      • Packet Classifier based on ALE engine with 512 classifiers
      • Priority based flow control
      • Time sensitive networking (TSN) support
      • Four CPU H/W interrupt Pacing
      • IP/UDP/TCP checksum offload in hardware
    • Two USB2.0 Ports
      • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
      • Integrated USB VBUS detection
      • Trace over USB supported
  • General Connectivity:
    • 9x Universal Asynchronous Receiver-Transmitters (UART)
    • 5x Serial Peripheral Interface (SPI) controllers
    • 6x Inter-Integrated Circuit (I2C) ports
    • 3x Multichannel Audio Serial Ports (McASP)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
      • Support for audio reference output clock
    • 3x enhanced PWM modules (ePWM)
    • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
    • 3x enhanced Capture modules (eCAP)
    • General-Purpose I/O (GPIO), All LVMOS I/O can be configured as GPIO
    • 3x Controller Area Network (CAN) modules with CAN-FD support
In-Stock: 137
137 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 25.5323$ 25.53
10+$ 24.3195$ 243.20
30+$ 22.218$ 666.54
119+$ 20.3857$ 2425.90
Standard Packaging119/Full Tray
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