XINLUDA XD74LS90

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a there-stage binary counter for which the count cycle length is divide-by-five for the 74LS90, and the divide-by-eight for the 74LS93. All of these counters have a gated zero reset and the ’LS90 also have gated set-to-nine inputs for use in BCD nine’s complement applications. To use their maximum count length (decade,divide-by-twelve,or four-bit binary) of these counters,the CKB input is connected to the QA output.The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table.A symmetrical divide-byten count can be obtained from the ’LS90 counters by connecting the QD output to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output QA.