The TMS48C128 and the TMS48C138 series are high-speed, 1 048 576-bit dynamic random-access memories organized as 131 072 words of eight bits each. They employ state-of-the-art EPlC (Enhanced Process Implanted CMos) technology for high performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 70 ns, 80 ns, and 100 ns. Maximum power dissipation is as low as 413 mW operating and 11 mW standby on 80 ns devices.
The EPIC technology permits operation from a single 5V supply, reducing system power supply and decoupling requirements, and easing board layout. Icc peaks are 140 mA typical, and a - 1-V input voltage undershoot can be tolerated, minimizing system noise considerations.
All inputs and outputs, including clocks, are compatible with Series 74TTL. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS48C128 and TMS48C138 are offered in a 300-mil 24/26-lead plastic surface mount SOJ (DJ suffix) package. This package is characterized for operation from 0°C to 70°C
TI TMS48C128-80DJ