ADI HMC7044LP10BE

HMC7044 is a high-performance dual-loop integer-N jitter attenuator capable of reference selection and ultra-low phase noise frequency generation, supporting high-speed data converters with parallel or serial (JESD204B) interfaces. It features two SPI-selectable integer-mode PLLs with overlapping on-chip VCOs offering tuning ranges of 2.5 GHz and 3 GHz respectively. The device is designed to meet the requirements of GSM and LTE base station designs, simplifying clock tree design for baseband and radio cards through a variety of clock management and distribution features. Fourteen low-noise configurable outputs provide flexible interfacing with many different devices, including data converters, FPGAs, and mixer LOs. The HMC7044's DCLK and SYSREF clock outputs are configurable to support CML, LVDS, LVPECL, and LVCMOS signaling standards, with different bias settings to compensate for varying PCB insertion loss.

• Ultra-low rms jitter: typical 44 fs (12 kHz to 20 MHz, 2457.6 MHz); noise floor: −156 dBc/Hz (2457.6 MHz)
• Low phase noise: −141.7 dBc/Hz (at 800 kHz, 983.04 MHz output)
• PLL2 provides up to 14 LVDS, LVPECL, or CML device clocks (DCLK)
• Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequencies
• Individually programmable delay
• Phase noise vs. power consumption programmable via SPI
• SYSREF valid interrupts simplify JESD204B synchronization
• Narrow-band, dual-core VCO
• Up to 2 buffered VCXO outputs
• Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes
• Frequency holdover mode maintains output frequency
• Loss of signal (LOS) detection and hitless reference switching
• 4 GPIO alarm/status indicators for system health monitoring
• Supports external VCO input up to 6000 MHz
• On-chip regulators provide excellent PSRR
• 68-pin, 10 mm × 10 mm LFCSP package

• JESD204B clock generation
• Cellular infrastructure (multi-carrier GSM, LTE, W-CDMA)
• Data converter clocking
• Microwave baseband cards
• Phased array reference distribution