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TI TPS54821RHLRRoHS

Manufacturer
MPN
TPS54821RHLR
LCSC Part #
C57461
Packaging
VQFN-14-EP(3.5x3.5)
Customer #
Key Attributes
4.5V to 17V Input, 8A Synchronous Buck Converter
Datasheetpdf iconTI TPS54821RHLR
In-Stock: 9,029
9,029 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 1.7116$ 1.71
10+$ 1.4193$ 14.19
30+$ 1.2586$ 37.76
100+$ 1.0783$ 107.83
500+$ 0.8997$ 449.85
1,000+$ 0.864$ 864.00
Standard Packaging3000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Power Management (PMIC)/Voltage Regulators - DC DC Switching Regulators
ManufacturerTI
PackagingVQFN-14-EP(3.5x3.5)
Operating Temperature-40℃~+125℃@(TJ)
Frequency - Switching1.6MHz
FunctionStep-down type
Number of Outputs1
FeaturesAdjustable soft-start;Operating status indication;Cycle-by-cycle current limiting;Hiccup current limiting;Frequency synchronization
Output TypeAdjustable
TopologyBuck
Operating Voltage4.5V~17V
Switch tube (built-in/external)Built-in
Output Voltage600mV~15V
Output Current8A
Quiescent Current600uA

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging3000
Sales UnitPiece

Introduction

AI Translation

The TPS54821 in a heat-enhanced 3.5 mm × 3.5 mm QFN package is a full-featured 17 V, 8 A synchronous buck converter. With high efficiency and integrated high-side/low-side MOSFETs, this buck converter is optimized for compact designs. Current mode control reduces component count, and selecting a high switching frequency shrinks the inductor footprint, enabling further space savings.

Output voltage startup soft-start ramp is controlled by the SS/TR pin, supporting both independent power supply mode and tracking mode. Power sequencing can also be achieved through proper configuration of the enable pin and the open-drain power good pin.

Cycle-by-cycle current limiting on the high-side FET protects the device from damage under overload conditions, further enhanced by a low-side source current limit that prevents current shoot-through. Additionally, a low-side sink current limit shuts off the low-side MOSFET to prevent excessive reverse current. When an overload current condition persists beyond a preset time, hiccup protection is triggered. When the die temperature exceeds the thermal shutdown threshold, the over-temperature hiccup protection disables the device, and the part is re-enabled after the built-in thermal shutdown hiccup interval.

The device is a 17-V, 8-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to 1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also has an internal phase lock loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge of an external system clock.

The device has been designed for safe monotonic startup into pre-biased loads. The default start up is when VIN is typically 4.0 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to operate with the internal pull-up current. The total operating current for the device is approximately 600 μA when not switching and under no load. When the device is disabled, the supply current is typically less than 2 μA.

The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 8 amperes. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.

The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to recharge the boot capacitor. The device can operate at 100% duty cycle as long as the boot capacitor voltage is higher than the preset BOOT-PH UVLO threshold which is typically 2.1V. The output voltage can be stepped down to as low as the 0.6V voltage reference (Vref).

The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage is less than 92% or greater than 106% of the reference voltage Vref and asserts high when the VSENSE pin voltage is 94% to 104% of the Vref.

The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical power supply s

Features

AI Translation
  • Integrated ±26 mΩ / 19 mΩ MOSFETs
  • Separate power rail: PVIN from 1.6 V to 17 V
  • 200 kHz to 1.6 MHz switching frequency
  • Synchronizable to external clock
  • 0.6 V ±1% reference voltage across temperature
  • 2 μA low shutdown quiescent current
  • Monotonic startup into pre-biased output
  • Operating junction temperature range: -40℃ to 125℃
  • Adjustable soft-start/power sequencing
  • Power-good output monitoring for undervoltage and overvoltage
  • Adjustable input undervoltage lockout

Applications

AI Translation
  • Digital TV power supply
  • Set-top box
  • Blu-ray DVD
  • High-performance point-of-load regulation design for home terminals