Intel/Altera EP3SE110F1152C3G

The Stratix III family offers one of the most architecturally advanced, high-performance, low-power FPGAs on the market. The family reduces power consumption through innovative programmable power technology, which enables performance when needed and reduces power on unused blocks. Optional core voltages and the latest silicon process optimizations are also employed to deliver the industry's lowest-power, high-performance FPGAs. Designed for ease of use and rapid system integration, the family offers two variants optimized for different application requirements: the Stratix III L series provides a balanced ratio of logic, memory, and multiplier resources for mainstream applications; the Stratix III E series targets data-centric applications with more abundant memory and multiplier resources. Modular I/O banks featuring a vertically migratable universal architecture deliver efficiency and flexibility for high-speed I/O. Package and die enhancements — including dynamic on-chip termination, output delay, and drive strength control — provide industry-leading signal integrity. Based on a 1.1V, 65nm all-layer copper SRAM process, the Stratix III family serves as a programmable alternative to custom ASICs and programmable processors in high-performance logic, DSP, and embedded designs. Stratix III devices include optional configuration bitstream security via volatile or non-volatile 256-bit AES encryption. For applications requiring ultra-high reliability, Stratix III devices incorporate automatic error detection circuitry to detect data corruption caused by soft errors in configuration RAM and user memory cells.

• 48,000 to 338,000 equivalent logic elements
• 2,430 to 20,497 Kbits enhanced TriMatrix memory comprising three RAM block sizes, enabling true dual-port memory and FIFO buffers
• High-speed DSP blocks supporting 9×9, 12×12, 18×18, and 36×36 multipliers (up to 550 MHz), multiply-accumulate functions, and dedicated FIR filter implementations
• I/O:GND:power ratio of 8:1:1, combined with on-chip and in-package decoupling for robust signal integrity
• Programmable power technology minimizing power consumption while maximizing device performance
• Optional core voltage available in low-voltage devices, supporting selection of lowest-power or highest-performance operation
• Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device
• Up to 12 PLLs per device with PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis, and dynamic phase shifting
• All I/O banks support memory interfaces with dedicated data strobe logic
• High-speed external memory interface support including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and enhanced QDR II SRAM, with up to 24 modular I/O banks
• Up to 1,104 user I/O pins arranged in 24 modular I/O banks, supporting a wide range of industry I/O standards
• Dynamic on-chip termination with auto-calibration supported across all I/O banks
• High-speed differential I/O with serializer/deserializer circuits and dynamic phase alignment circuits at 1.6 Gbps
• High-speed networking and communication bus standard support including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI
• High-density, high-performance FPGA supporting 256-bit AES volatile and non-volatile security keys for design protection
• Robust on-chip hot-socketing and power sequencing support
• Integrated CRC for configuration memory error detection with critical error determination for high-availability systems
• Built-in ECC circuitry for detecting and correcting data errors in M144K TriMatrix memory blocks
• Nios II embedded processor support
• Support for multiple IP megafunctions from Altera MegaCore functions and the Altera Megafunction Partners Program

• Mainstream Applications
• Data-centric Applications
• Wireless Applications
• Medical Imaging