AMD/XILINX XC3S400A-4FTG256C

The Spartan-3A family of Field-Programmable Gate Arrays (FPGAs) solves the design challenges in most high-volume, cost-sensitive, I/O-intensive electronic applications. The five-member family offers densities ranging from 50,000 to 1.4 million system gates. The Spartan-3A FPGAs are part of the Extended Spartan-3A family, which also include the non-volatile Spartan-3AN and the higher density Spartan-3A DSP FPGAs. The Spartan-3A family builds on the success of the earlier Spartan-3E and Spartan-3 FPGA families. New features improve system performance and reduce the cost of configuration. These Spartan-3A family enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in the programmable logic industry. Because of their exceptionally low cost, Spartan-3A FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment. The Spartan-3A family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, lengthy development cycles, and the inherent inflexibility of conventional ASICs, and permit field design upgrades.

• Very low cost, high-performance logic solution for high-volume, cost-conscious applications
• Dual-range VCCAUX supply simplifies 3.3V-only design
• Suspend, Hibernate modes reduce system power
• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 502 I/O pins or 227 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• Selectable output drive, up to 24 mA per pin
• QUIETIO standard reduces 1/O switching noise
• Full 3.3V±10% compatibility and hot swap compliance
• 640+ Mb/s data transfer rate per differential I/O
• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors
• Enhanced Double Data Rate (DDR) support
• DDR/DDR2 SDRAM support up to 400 Mb/s
• Fully compliant 32-/64-bit, 33/66 MHz PCI technology support
• Densities up to 25,344 logic cells, including optional shift register or distributed RAM support
• Efficient wide multiplexers, wide logic
• Fast look-ahead carry logic
• Enhanced 18×18 multipliers with optional pipeline
• IEEE 1149.1/1532 JTAG programming/debug port
• Up to 576 Kbits of fast block RAM with byte write enables for processor applications
• Up to 176 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 320 MHz)
• Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing
• Low-cost, space-saving SPI serial Flash PROM x8 or x8/x16 BPI parallel NOR Flash PROM
• Low-cost Xilinx Platform Flash with JTAG
• Unique Device DNA identifier for design authentication
• Load multiple bitstreams under FPGA control
• Post-configuration CRC checking

• broadband access
• home networking
• display/projection
• digital television equipment