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Intel/Altera EP3C5F256C8N
| Manufacturer | |
| MPN | EP3C5F256C8N |
| LCSC Part # | C569008 |
| Packaging | FBGA-256 |
| Customer # | |
| Key Attributes | 5136 321 FBGA-256 FPGAs (Field Programmable Gate Array) RoHS |
| Datasheet |  Intel/Altera EP3C5F256C8N |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | Intel/Altera | |
| Packaging | FBGA-256 | |
| Embedded Block RAM | 423936bit | |
| Voltage - Supply(VCCIO) | - | |
| Number of Logic Elements/Blocks | 5136 | |
| Logic Array Blocks | 321 | |
| Operating Temperature | 0℃~+85℃ | |
| Type | - |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 90 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Lowest Power FPGAs
- Design Security Feature
- Increased System Integration
- LE Features
- Control Signals
- Parity Bit Support
- Byte Enable Support
- Packed Mode Support
- Address Clock Enable Support
- Mixed-Width Support
- Asynchronous Clear
- Memory Modes
- Clocking Modes
- Embedded Multiplier Block Overview
- Architecture
- Operational Modes
- Clock Networks
- GCLK Network
- Clock Control Block
- GCLK Network Clock Source Generation
- GCLK Network Power Down
- clkena Signals
- Cyclone III Device Family PLL Hardware Overview
- External Clock Outputs
- Clock Feedback Modes
- Hardware Features
- Clock Multiplication and Division
- Post-Scale Counter Cascading
- Programmable Duty Cycle
- PLL Control Signals
- Clock Switchover
- Automatic Clock Switchover
- Manual Override
- Manual Clock Switchover
- Guidelines
- Programmable Bandwidth
- Phase Shift Implementation
- PLL Cascading
- PLL Reconfiguration
- PLL Reconfiguration Hardware Implementation
- Post-Scale Counters (C0 to C4)
- Scan Chain Description
- Charge Pump and Loop Filter
- Bypassing PLL Counter
- Dynamic Phase Shifting
- Spread-Spectrum Clocking
- Cyclone III Device Family I/O Elements
- I/O Element Features
- Programmable Current Strength
- Slew Rate Control
- Open-Drain Output
- Bus Hold
- Programmable Pull-Up Resistor
- Programmable Delay
- PCI-Clamp Diode
- LVDS Transmitter Programmable Pre-Emphasis
- OCT Support
- On-Chip Series Termination with Calibration
- On-Chip Series Termination Without Calibration
- I/O Standards
- Termination Scheme for I/O Standards
- Voltage-Referenced I/O Standard Termination
- Differential I/O Standard Termination
- I/O Banks
- High-Speed Differential Interfaces
- External Memory Interfacing
- Pad Placement and DC Guidelines
- Pad Placement
- DC Guidelines
- High-Speed I/O Interface
- High-Speed I/O Standards Support
- LVDS I/O Standard Support in the Cyclone III Device Family
- Designing with LVDS
- BLVDS I/O Standard Support in the Cyclone III Device Family
- Designing with BLVDS
- RSDS, Mini-LVDS, and PPDS I/O Standard Support in the Cyclone III Device Family
- Designing with RSDS, Mini-LVDS, and PPDS
- LVPECL I/O Support in the Cyclone III Device Family
- Differential SSTL I/O Standard Support in the Cyclone III Device Family
- Differential HSTL I/O Standard Support in the Cyclone III Device Family
- True Output Buffer Feature
- Programmable Pre-Emphasis
- High-Speed I/O Timing
- Design Guidelines
- Differential Pad Placement Guidelines
- Board Design Considerations
- Software Overview
- Cyclone III Device Family Memory Interfaces Pin Support
- Data and Data Clock/Strobe Pins
- Optional Parity, DM, and Error Correction Coding Pins
- Address and Control/Command Pins
- Memory Clock Pins
- Cyclone III Device Family Memory Interfaces Features
- DDR Input Registers
- DDR Output Registers
- OCT
- PLL
In-Stock: 31
31 In stock, ships now
Add to BOM List
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 28.0099 | $ 28.01 |
| 30+ | $ 26.5418 | $ 796.25 |
Standard Packaging90/Full Tray | ||
Better price for more quantity?
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | Intel/Altera | |
| Packaging | FBGA-256 | |
| Embedded Block RAM | 423936bit | |
| Voltage - Supply(VCCIO) | - | |
| Number of Logic Elements/Blocks | 5136 | |
| Logic Array Blocks | 321 | |
| Operating Temperature | 0℃~+85℃ | |
| Type | - |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 90 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Lowest Power FPGAs
- Design Security Feature
- Increased System Integration
- LE Features
- Control Signals
- Parity Bit Support
- Byte Enable Support
- Packed Mode Support
- Address Clock Enable Support
- Mixed-Width Support
- Asynchronous Clear
- Memory Modes
- Clocking Modes
- Embedded Multiplier Block Overview
- Architecture
- Operational Modes
- Clock Networks
- GCLK Network
- Clock Control Block
- GCLK Network Clock Source Generation
- GCLK Network Power Down
- clkena Signals
- Cyclone III Device Family PLL Hardware Overview
- External Clock Outputs
- Clock Feedback Modes
- Hardware Features
- Clock Multiplication and Division
- Post-Scale Counter Cascading
- Programmable Duty Cycle
- PLL Control Signals
- Clock Switchover
- Automatic Clock Switchover
- Manual Override
- Manual Clock Switchover
- Guidelines
- Programmable Bandwidth
- Phase Shift Implementation
- PLL Cascading
- PLL Reconfiguration
- PLL Reconfiguration Hardware Implementation
- Post-Scale Counters (C0 to C4)
- Scan Chain Description
- Charge Pump and Loop Filter
- Bypassing PLL Counter
- Dynamic Phase Shifting
- Spread-Spectrum Clocking
- Cyclone III Device Family I/O Elements
- I/O Element Features
- Programmable Current Strength
- Slew Rate Control
- Open-Drain Output
- Bus Hold
- Programmable Pull-Up Resistor
- Programmable Delay
- PCI-Clamp Diode
- LVDS Transmitter Programmable Pre-Emphasis
- OCT Support
- On-Chip Series Termination with Calibration
- On-Chip Series Termination Without Calibration
- I/O Standards
- Termination Scheme for I/O Standards
- Voltage-Referenced I/O Standard Termination
- Differential I/O Standard Termination
- I/O Banks
- High-Speed Differential Interfaces
- External Memory Interfacing
- Pad Placement and DC Guidelines
- Pad Placement
- DC Guidelines
- High-Speed I/O Interface
- High-Speed I/O Standards Support
- LVDS I/O Standard Support in the Cyclone III Device Family
- Designing with LVDS
- BLVDS I/O Standard Support in the Cyclone III Device Family
- Designing with BLVDS
- RSDS, Mini-LVDS, and PPDS I/O Standard Support in the Cyclone III Device Family
- Designing with RSDS, Mini-LVDS, and PPDS
- LVPECL I/O Support in the Cyclone III Device Family
- Differential SSTL I/O Standard Support in the Cyclone III Device Family
- Differential HSTL I/O Standard Support in the Cyclone III Device Family
- True Output Buffer Feature
- Programmable Pre-Emphasis
- High-Speed I/O Timing
- Design Guidelines
- Differential Pad Placement Guidelines
- Board Design Considerations
- Software Overview
- Cyclone III Device Family Memory Interfaces Pin Support
- Data and Data Clock/Strobe Pins
- Optional Parity, DM, and Error Correction Coding Pins
- Address and Control/Command Pins
- Memory Clock Pins
- Cyclone III Device Family Memory Interfaces Features
- DDR Input Registers
- DDR Output Registers
- OCT
- PLL
C569008 EasyEDA Library
Not drawn yet
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |