XTX XT61M4G8D2TA-B8BEA

XTX nMCP is a Multi-Chip Packaged memory which combines NAND flash memory and LPDDR2 (Low Power Double Data Rate) SDRAM. The NAND flash memory provides the most cost-effective solution for the non-volatile solid state mass storage market, while the LPDDR2 is an excellent solution for large volatile but fast storage applications such as random/temporary data access. XTX nMCP is suitable for use in data memory of portable electronic devices to reduce its square size and power consumption at the same time. The NAND flash memory and LPDDR2 SDRAM in it could be operated individually.

• Single Level per Cell (SLC) Technology
• ECC requirement: 8bit/512Bytes
• Power Supply Voltage Voltage range: 1.7V ~ 1.95V
• Page size: x8 (4096 + 256) bytes; 256 - bytes spare area
• Block size: x8 (256k + 16k) bytes
• Plane size: 1024 Blocks per Plane
• Modes: Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
• Random access: 25 µs (Max)
• Sequential access: 25ns(Min)(CL = 30pF)
• Program time / Multiplane Program time: 300 µs (Typ.)
• Block Erase time: 3.5 ms (Typ.)
• 10 Year Data retention (Typ.)
• Blocks 0 is guaranteed to be a valid block at the time of shipment.
• Density: 2G bits Organization x 32 bits: 8M words x 32 bits x 8 banks
• Power supply – VDD1 = 1.70V to 1.95V – VDD2, VDDCA, VDQ = 1.14V to 1.30V
• Clock frequency: 533/466/400/333/266/200/166Mhz(max.)
• 2KB page size
• Row address: R0 to R13
• Column address: C0 to C8 (32 bits)
• Eight internal banks for concurrent operation
• Interface: HSUL_12
• Burst lengths (BL): 4, 8, 16
• Burst type (BT) – Sequential (4, 8, 16) – Interleave (4, 8)
• Read latency (RL): 3, 4, 5, 6, 7, 8
• Write latency (WL): 1, 2, 3, 4
• Pre - charge: auto pre - charge option for each burst access
• Programmable driver strength
• Refresh: auto - refresh, self - refresh
• Refresh cycles: 16384 cycles/64ms
• Average refresh period: 3.9us
• DLL is not implemented
• Low power consumption
• JEDEC LPDDR2 - S4B compliance
• Partial Array Self - Refresh (PASR)
• Auto Temperature Compensated Self - Refresh (ATCSR) by built - in temperature sensor
• Deep power - down mode
• Double - data - rate architecture; two data transfers per one clock cycle
• The high - speed data transfer is realized by the 4 bits pre - fetch pipelined architecture
• Differential clock inputs (CK and /CK)
• Commands entered on both rising and falling CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data