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XTX XT61M2G8D2TA-B8BEA product image
  • XT61M2G8D2TA-B8BEA thumbnail 1
  • XT61M2G8D2TA-B8BEA thumbnail 2
  • XT61M2G8D2TA-B8BEA thumbnail 3
  • Pinout Diagram
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XTX XT61M2G8D2TA-B8BEARoHS

Manufacturer
XTXAsian Brands
MPN
XT61M2G8D2TA-B8BEA
LCSC Part #
C558831
Packaging
BGA-162(8x10.5)
Customer #
Key Attributes
2Gb NAND flash + 2Gb Low Power DDR2 SDRAM
Datasheetpdf iconXTX XT61M2G8D2TA-B8BEA
In-Stock: 242
242 In stock, ships now
Add to BOM List
QtyUnit PriceTotal Amount
1+$ 19.28$ 15.4240$ 15.42
10+$ 19.0183$ 15.2147$ 152.15
30+$ 18.5631$ 14.8505$ 445.52
100+$ 18.1681$ 14.5345$ 1453.45
Standard Packaging242/Full Tray
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Memory/Memory (ICs)
ManufacturerXTX
PackagingBGA-162(8x10.5)
Voltage - Supply-
Operating temperature-
Clock Frequency-

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging242
Sales UnitPiece

Introduction

AI Translation

XTX nMCP is a Multi-Chip Packaged memory which combines NAND flash memory and LPDDR2 (Low Power Double Data Rate) SDRAM. The NAND flash memory provides the most cost-effective solution for the non-volatile solid state mass storage market, while the LPDDR2 is an excellent solution for large volatile but fast storage applications such as random/temporary data access. XTX nMCP is suitable for use in data memory of portable electronic devices to reduce its square size and power consumption at the same time. The NAND flash memory and LPDDR2 SDRAM in it could be operated individually.

Features

AI Translation
  • DLL is not implemented
  • Low power consumption
  • JEDEC LPDDR2-S4B compliance
  • Partial Array Self-Refresh (PASR)
  • Bank Masking
  • Auto Temperature Compensated Self-Refresh (ATCSR) by built-in temperature sensor
  • Deep power-down mode
  • Double-data-rate architecture; two data transfers per one clock cycle
  • The high-speed data transfer is realized by the 4 bits pre-fetch pipelined architecture
  • Differential clock inputs (CK and /CK)
  • Commands entered on both rising and falling CK edge; data and data mask referenced to both edges of DQS
  • Data mask (DM) for write data