PHILIPS 74F377AD

The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. The E input must be stable one setup time prior to the Low-to-High clock transition for predictable operation.

• High impedance inputs for reduced loading (20μA in Low and High states)
• Ideal for addressable register applications
• Enable for address and data synchronization applications
• Eight edge–triggered D–type flip–flops
• Buffered common clock