Nexperia 74AHC273BQ,115
| Manufacturer | |
| MPN | 74AHC273BQ,115 |
| LCSC Part # | C554341 |
| Packaging | DHVQFN-20-EP(2.5x4.5) |
| Customer # | |
| Key Attributes | Octal D-type flip-flop with reset; positive-edge trigger |
| Datasheet |  Nexperia 74AHC273BQ,115 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-20-EP(2.5x4.5) | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 2V~5.5V | |
| Number of Bits per Element | 8 | |
| Series | 74AHC Series | |
| Output Type | - | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Quiescent Current | 4uA | |
| Setup Time | 3ns | |
| Hold Time | 1ns | |
| Propagation Delay | 11ns@5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74AHC273; 74AHCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
Features
- Wide supply voltage range from 2.0 to 5.5 V
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- CMOS low power dissipation
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Ideal buffer for MOS microcontroller or memory
- Common clock and master reset
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
- Input levels: For 74AHC273: CMOS level For 74AHCT273: TTL level
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 0.5852 | $ 0.59 |
| 10+ | $ 0.4999 | $ 5.00 |
| 30+ | $ 0.4642 | $ 13.93 |
| 100+ | $ 0.4176 | $ 41.76 |
| 500+ | $ 0.3974 | $ 198.70 |
| 1,000+ | $ 0.385 | $ 385.00 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-20-EP(2.5x4.5) | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 2V~5.5V | |
| Number of Bits per Element | 8 | |
| Series | 74AHC Series | |
| Output Type | - | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Quiescent Current | 4uA | |
| Setup Time | 3ns | |
| Hold Time | 1ns | |
| Propagation Delay | 11ns@5V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74AHC273; 74AHCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
Features
- Wide supply voltage range from 2.0 to 5.5 V
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- CMOS low power dissipation
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Ideal buffer for MOS microcontroller or memory
- Common clock and master reset
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
- Input levels: For 74AHC273: CMOS level For 74AHCT273: TTL level
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |