TI CDCE913QPWRQ1

The CDCE913-Q1 and CDCEL913-Q1 devices are modular, phase-locked loop (PLL) based programmable clock synthesizers. These devices provide flexible and programmable options, such as output clocks, input signals, and control pins, so that the user can configure the CDCEx913-Q1 for their own specifications. The CDCEx913-Q1 generates up to three output clocks from a single input frequency to enable both board space and cost savings. Additionally, with multiple outputs, the clock generator can replace multiple crystals with one clock generator. This makes the device well-suited for head unit and telematics applications in infotainment and camera systems in ADAS as these platforms are evolving into smaller and more cost effective systems. Furthermore, each output can be programmed in-system for any clock frequency up to 230 MHz through the integrated, configurable PLL. The PLL also supports spread-spectrum clocking (SSC) with programmable down and center spread. This provides better electromagnetic interference (EMI) performance to enable customers to pass industry standards such as CISPR-25. Customization of frequency programming and SSC are accessed using three, user-defined control pins. This eliminates the need to use an additional interface to control the clock. Specific power-up and power-down sequences can also be defined to the user’s needs.

• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
  • Device Temperature Grades
    • Grade 1 For CDCE913-Q1: -40°C to +125°C Ambient Operating Temperature
    • Grade 3 For CDCEL913-Q1: -40°C to +85°C Ambient Operating Temperature
  • Device HBM ESD Classification Level H2
  • Device CDM ESD Classification Level C6
• In-System Programmability and EEPROM
  • Serial Programmable Volatile Register
  • Nonvolatile EEPROM to Store Customer Settings
• Flexible Input Clocking Concept
  • External Crystal: 8 MHz to 32 MHz
  • On-Chip VCXO: Pull Range ±150 ppm
  • Single-Ended LVCMOS up to 160 MHz
• Free Selectable Output Frequency up to 230 MHz
• Low-Noise PLL Core
  • PLL Loop Filter Components Integrated
  • Low Period Jitter (Typical 50 ps)
• Separate Output Supply Pins
  • CDCE913-Q1: 3.3 V and 2.5 V
  • CDCEL913-Q1: 1.8 V
• Flexible Clock Driver
  • Three User-Definable Control Inputs [S0, S1, S2], for Example, SSC Selection, Frequency Switching, Output Enable, or Power Down
  • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet, and GPS
  • Generates Common Clock Frequencies Used With TI-DaVinci, OMAP, DSPs
  • Programmable SSC Modulation
  • Enables 0-PPM Clock Generation
• 1.8-V Device Power Supply
• Packaged in TSSOP Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock)

• Clusters
• Head Units
• Navigation Systems
• Advanced Driver Assistance Systems (ADAS)