Nexperia 74LVT573BQ,115
| Manufacturer | |
| MPN | 74LVT573BQ,115 |
| LCSC Part # | C549054 |
| Packaging | DHVQFN-20-EP(2.5x4.5) |
| Customer # | |
| Key Attributes | D Latch 2.7V~3.6V 8 4.3ns DHVQFN-20-EP(2.5x4.5) Latches RoHS |
| Datasheet |  Nexperia 74LVT573BQ,115 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-20-EP(2.5x4.5) | |
| Series | 74LVT | |
| Logic Type | D Latch | |
| Voltage - Supply | 2.7V~3.6V | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 32mA | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 32mA | |
| Number of Channels | 8 | |
| Setup Time | 0.7ns | |
| Hold Time | 1.6ns | |
| Propagation Delay | 4.3ns |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs
Features
- Wide supply voltage range from 2.7 to 3.6 V
- Inputs and outputs arranged for easy interfacing to microprocessors
- 3-state outputs for bus interfacing
- Common output enable control
- Overvoltage tolerant inputs to 5.5 V
- BiCMOS high speed and output drive
- Direct interface with TTL levels
- Input and output interface capability to systems at 5 V supply
- Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
- Live insertion and extraction permitted
- No bus current loading when output is tied to 5 V bus
- Power-up reset
- Power-up 3-state
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
- Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 ℃ to +85 ℃
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 0.9061 | $ 0.91 |
| 200+ | $ 0.352 | $ 70.40 |
| 500+ | $ 0.3396 | $ 169.80 |
| 1,000+ | $ 0.3334 | $ 333.40 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Latches | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-20-EP(2.5x4.5) | |
| Series | 74LVT | |
| Logic Type | D Latch | |
| Voltage - Supply | 2.7V~3.6V | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 32mA | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 32mA | |
| Number of Channels | 8 | |
| Setup Time | 0.7ns | |
| Hold Time | 1.6ns | |
| Propagation Delay | 4.3ns |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs
Features
- Wide supply voltage range from 2.7 to 3.6 V
- Inputs and outputs arranged for easy interfacing to microprocessors
- 3-state outputs for bus interfacing
- Common output enable control
- Overvoltage tolerant inputs to 5.5 V
- BiCMOS high speed and output drive
- Direct interface with TTL levels
- Input and output interface capability to systems at 5 V supply
- Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
- Live insertion and extraction permitted
- No bus current loading when output is tied to 5 V bus
- Power-up reset
- Power-up 3-state
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
- Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 ℃ to +85 ℃
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |