Nexperia 74LVC574ABQ,115
| Manufacturer | |
| MPN | 74LVC574ABQ,115 |
| LCSC Part # | C548820 |
| Packaging | DHVQFN-20-EP(2.5x4.5) |
| Customer # | |
| Key Attributes | Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state |
| Datasheet |  Nexperia 74LVC574ABQ,115 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-20-EP(2.5x4.5) | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 1.65V~3.6V | |
| Number of Bits per Element | 8 | |
| Series | 74LVC Series | |
| Output Type | Tri-State | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 2ns | |
| Quiescent Current | 100nA | |
| Hold Time | 1.5ns | |
| Propagation Delay | 3.5ns@3.3V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC574A is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.2 to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- Overvoltage tolerant inputs to 5.5 V
- High-impedance when V(CC)=0 V
- 8-bit positive edge-triggered register
- Independent register and 3-state buffer operation
- Flow-through pin-out architecture
- IOFF circuitry provides partial Power-down mode operation
- Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.6058 | $ 0.61 |
| 10+ | $ 0.4898 | $ 4.90 |
| 30+ | $ 0.4318 | $ 12.95 |
| 100+ | $ 0.3754 | $ 37.54 |
| 500+ | $ 0.34 | $ 170.00 |
| 1,000+ | $ 0.3223 | $ 322.30 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-20-EP(2.5x4.5) | |
| Operating Temperature | -40℃~+125℃ | |
| Voltage - Supply | 1.65V~3.6V | |
| Number of Bits per Element | 8 | |
| Series | 74LVC Series | |
| Output Type | Tri-State | |
| Number of Elements | 1 | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 2ns | |
| Quiescent Current | 100nA | |
| Hold Time | 1.5ns | |
| Propagation Delay | 3.5ns@3.3V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC574A is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.2 to 3.6 V
- CMOS low power consumption
- Direct interface with TTL levels
- Overvoltage tolerant inputs to 5.5 V
- High-impedance when V(CC)=0 V
- 8-bit positive edge-triggered register
- Independent register and 3-state buffer operation
- Flow-through pin-out architecture
- IOFF circuitry provides partial Power-down mode operation
- Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |