Nexperia 74LVC2G38GT,115
| Manufacturer | |
| MPN | 74LVC2G38GT,115 |
| LCSC Part # | C548659 |
| Packaging | XSON-8(1x2) |
| Customer # | |
| Key Attributes | 4uA 1.65V~5.5V 3.3ns@5V,50pF XSON-8(1x2) Gates and Inverters RoHS |
| Datasheet |  Nexperia 74LVC2G38GT,115 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | XSON-8(1x2) | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - Low | 700mV;800mV | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - High | 1.7V~2V | |
| Logic Family | 74LVC Series | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 4uA | |
| Voltage - Supply | 1.65V~5.5V | |
| Current - Output High(IOH) | - | |
| Number of Channels | 2;2 | |
| Output Logic Level - Low | 100mV;450mV;300mV;400mV;550mV | |
| Propagation Delay | 3.3ns@5V,50pF | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 5000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G38 is a dual 2-input NAND gate with open-drain outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.65 V to 5.5 V
- 5 V tolerant outputs for interfacing with 5 V logic
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- CMOS low power dissipation
- IOFF circuitry provides partial Power-down mode operation
- ±24 mA output drive (VCC = 3.0 V)
- Open-drain outputs
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
Applications
- Level translation in mixed 3.3V and 5V environments
- Interface with 5V logic
- Direct TTL-level interface
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.2541 | $ 0.25 |
| 10+ | $ 0.2493 | $ 2.49 |
| 30+ | $ 0.2445 | $ 7.34 |
| 100+ | $ 0.2413 | $ 24.13 |
Standard Packaging5000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | XSON-8(1x2) | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - Low | 700mV;800mV | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - High | 1.7V~2V | |
| Logic Family | 74LVC Series | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 4uA | |
| Voltage - Supply | 1.65V~5.5V | |
| Current - Output High(IOH) | - | |
| Number of Channels | 2;2 | |
| Output Logic Level - Low | 100mV;450mV;300mV;400mV;550mV | |
| Propagation Delay | 3.3ns@5V,50pF | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 5000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G38 is a dual 2-input NAND gate with open-drain outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.65 V to 5.5 V
- 5 V tolerant outputs for interfacing with 5 V logic
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- CMOS low power dissipation
- IOFF circuitry provides partial Power-down mode operation
- ±24 mA output drive (VCC = 3.0 V)
- Open-drain outputs
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and -40 °C to +125 °C
Applications
- Level translation in mixed 3.3V and 5V environments
- Interface with 5V logic
- Direct TTL-level interface
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |