Nexperia 74LVC2G02GT,115
| Manufacturer | |
| MPN | 74LVC2G02GT,115 |
| LCSC Part # | C548543 |
| Packaging | XSON-8(1x2) |
| Customer # | |
| Key Attributes | Dual 2-input NOR gate |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | XSON-8(1x2) | |
| Logic Family | 74LVC Series | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | 100mV;450mV;300mV;400mV;550mV | |
| Propagation Delay | 4.3ns@5V,50pF | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - Low | 700mV~800mV | |
| Input Logic Level - High | 1.7V~2V | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | 1.2V;1.9V;2.2V;2.3V;3.8V | |
| Quiescent Current(Iq) | 4uA | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 5000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G02 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.65 V to 5.5 V
- 5 V tolerant outputs for interfacing with 5 V logic
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- ±24 mA output drive (VCC = 3.0 V)
- CMOS low power consumption
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8-B/JESD36 (2.7 V to 3.6 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V; CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Applications
- Translator for mixed 3.3V and 5V environments
- Interface with 5V logic
- Direct interface with TTL levels
| Qty | Unit Price | Total Amount |
|---|---|---|
| 5+ | $ 0.1719 | $ 0.86 |
| 50+ | $ 0.1333 | $ 6.67 |
| 150+ | $ 0.1167 | $ 17.51 |
| 500+ | $ 0.0961 | $ 48.05 |
| 2,500+ | $ 0.0868 | $ 217.00 |
| 5,000+ | $ 0.0813 | $ 406.50 |
Standard Packaging5000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | XSON-8(1x2) | |
| Logic Family | 74LVC Series | |
| Voltage - Supply | 1.65V~5.5V | |
| Output Logic Level - Low | 100mV;450mV;300mV;400mV;550mV | |
| Propagation Delay | 4.3ns@5V,50pF | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - Low | 700mV~800mV | |
| Input Logic Level - High | 1.7V~2V | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - High | 1.2V;1.9V;2.2V;2.3V;3.8V | |
| Quiescent Current(Iq) | 4uA | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 32mA | |
| Current - Output Low(IOL) | 32mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 5000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G02 is a dual 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 1.65 V to 5.5 V
- 5 V tolerant outputs for interfacing with 5 V logic
- Overvoltage tolerant inputs to 5.5 V
- High noise immunity
- ±24 mA output drive (VCC = 3.0 V)
- CMOS low power consumption
- IOFF circuitry provides partial Power-down mode operation
- Latch-up performance exceeds 250 mA
- Direct interface with TTL levels
- Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8-B/JESD36 (2.7 V to 3.6 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V; CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Applications
- Translator for mixed 3.3V and 5V environments
- Interface with 5V logic
- Direct interface with TTL levels
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |



