Nexperia 74LVC273BQ,115
| Manufacturer | |
| MPN | 74LVC273BQ,115 |
| LCSC Part # | C548519 |
| Packaging | DHVQFN-20-EP(2.5x4.5) |
| Customer # | |
| Key Attributes | Octal D-type flip-flop with reset; positive-edge trigger |
| Datasheet |  Nexperia 74LVC273BQ,115 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-20-EP(2.5x4.5) | |
| Voltage - Supply | 1.65V~3.6V | |
| Number of Bits per Element | 8 | |
| Output Type | - | |
| Operating Temperature | -40℃~+125℃ | |
| Series | 74LVC Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Current - Output High(IOH) | 24mA | |
| Number of Elements | 1 | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 1ns | |
| Quiescent Current | 100nA | |
| Hold Time | 1ns | |
| Propagation Delay | 4.1ns@3.3V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
Features
- Wide supply voltage range from 1.2 V to 3.6 V
- Overvoltage tolerant inputs to 5.5 V
- CMOS low power consumption
- Direct interface with TTL levels
- Output drive capability 50 Ω transmission lines at +85 ℃
- Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V), JESD8-5A (2.3 V to 2.7 V), JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V; CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Applications
- Level translator for mixed 3.3V and 5V environments
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 1.8105 | $ 1.81 |
| 10+ | $ 1.5374 | $ 15.37 |
| 30+ | $ 1.3669 | $ 41.01 |
| 100+ | $ 1.1919 | $ 119.19 |
| 500+ | $ 1.1135 | $ 556.75 |
| 1,000+ | $ 1.0788 | $ 1078.80 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-20-EP(2.5x4.5) | |
| Voltage - Supply | 1.65V~3.6V | |
| Number of Bits per Element | 8 | |
| Output Type | - | |
| Operating Temperature | -40℃~+125℃ | |
| Series | 74LVC Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Current - Output High(IOH) | 24mA | |
| Number of Elements | 1 | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 1ns | |
| Quiescent Current | 100nA | |
| Hold Time | 1ns | |
| Propagation Delay | 4.1ns@3.3V,50pF | |
| Trigger Type | Rising Edge |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and data inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
Features
- Wide supply voltage range from 1.2 V to 3.6 V
- Overvoltage tolerant inputs to 5.5 V
- CMOS low power consumption
- Direct interface with TTL levels
- Output drive capability 50 Ω transmission lines at +85 ℃
- Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V), JESD8-5A (2.3 V to 2.7 V), JESD8-C/JESD36 (2.7 V to 3.6 V)
- ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V; CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Applications
- Level translator for mixed 3.3V and 5V environments
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |