LCSC Electronics logoLCSC Electronics svg logo
Sign In
USD
Cart
Nexperia 74LVC1G57GW,125 product image
  • 74LVC1G57GW,125 thumbnail 1
  • 74LVC1G57GW,125 thumbnail 2
  • 74LVC1G57GW,125 thumbnail 3
  • Pinout
  • Footprint
Images for reference only

Nexperia 74LVC1G57GW,125RoHS

Manufacturer
Nexperia
MPN
74LVC1G57GW,125
LCSC Part #
C548392
Packaging
TSSOP-6
Customer #
Key Attributes
Low-power configurable multiple function gate
Datasheetpdf iconNexperia 74LVC1G57GW,125
In-Stock: 2,795
2,795 In stock, ships now
Minimum: 5Multiple: 5Sales Unit: Piece
Add to BOM List
QtyUnit PriceTotal Amount
5+$ 0.2293$ 1.15
50+$ 0.1818$ 9.09
150+$ 0.1614$ 24.21
500+$ 0.136$ 68.00
3,000+$ 0.1247$ 374.10
6,000+$ 0.1179$ 707.40
Standard Packaging3000/Full Reel
Better price for more quantity?
$

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters - Multi-Function, Configurable
ManufacturerNexperia
PackagingTSSOP-6
output type-
Logic Family74LVC Series
Input typeSchmitt Trigger
Propagation Delay7.9ns@3.3V,50pF
Voltage - Supply1.65V~5.5V
Operating Temperature-40℃~+125℃
Output Logic Level - Low100mV~800mV
Input Logic Level - High-
Input Logic Level - Low-
Current - Output Low(IOL)32mA
Output Logic Level - High-
Quiescent Current(Iq)4uA
Current - Output High(IOH)32mA
FeaturesLocal shutdown mode;Overvoltage-tolerant input
Number of Gates1
Report an ErrorShow similar products (0) >

Introduction

AI Translation

The 74LVC1G57 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features

AI Translation
  • Wide supply voltage range from 1.65 V to 5.5 V
  • Overvoltage tolerant inputs to 5.5 V
  • High noise immunity
  • ±24 mA output drive (VCC = 3.0 V)
  • CMOS low power dissipation
  • Latch-up performance exceeds 250 mA
  • Direct interface with TTL levels
  • IOFF circuitry provides partial Power-down mode operation
  • Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8B/JESD36 (2.7 V to 3.6 V)
  • ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Multiple package options
  • Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

Applications

AI Translation
  • Level translator for mixed 3.3V and 5V environments