Nexperia 74LV14BQ,115
| Manufacturer | |
| MPN | 74LV14BQ,115 |
| LCSC Part # | C547900 |
| Packaging | DHVQFN-14-EP(2.5x3) |
| Customer # | |
| Key Attributes | Schmitt trigger 1V~5.5V 6 40uA DHVQFN-14-EP(2.5x3) Gates and Inverters RoHS |
| Datasheet |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-14-EP(2.5x3) | |
| Input Type | Schmitt trigger | |
| Logic Family | 74LV | |
| Voltage - Supply | 1V~5.5V | |
| Propagation Delay | 80ns;27ns;20ns;22ns@3V,15pF;18ns | |
| Output Logic Level - Low | 0V;200mV;500mV;650mV | |
| Features | Noise suppression function | |
| Input Logic Level - Low | - | |
| Input Logic Level - High | - | |
| Operating Temperature | -40℃~+125℃ | |
| Number of Circuits | 6 | |
| Output Logic Level - High | 1.2V;1.8V;2.5V;2.8V;4.3V;2.4V;3.6V | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | - | |
| Number of Channels | - | |
| Current - Output Low(IOL) | - |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14 and 74HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger input. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage V(T+) and the negative voltage V(T-) is defined as the input hysteresis voltage VH.
Features
- Wide supply voltage range from 1.0 V to 5.5 V
- CMOS low power dissipation
- Optimized for low voltage applications: 1.0 V to 3.6 V
- Accepts TTL input levels between V(CC)=2.7 V and V(CC)=3.6 V
- Typical output ground bounce <0.8 V at V(CC)=3.3 V and T(amb)=25 °C
- Typical HIGH-level output voltage (V(0H)) undershoot: >2 V at V(CC)=3.3 V and T(amb)=25 °C
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.5 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Applications
- Wave and pulse shapers for highly noisy environments
- Astable multivibrators
- Monostable multivibrators
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.353 | $ 0.35 |
| 10+ | $ 0.3465 | $ 3.47 |
| 30+ | $ 0.3416 | $ 10.25 |
| 100+ | $ 0.3351 | $ 33.51 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-14-EP(2.5x3) | |
| Input Type | Schmitt trigger | |
| Logic Family | 74LV | |
| Voltage - Supply | 1V~5.5V | |
| Propagation Delay | 80ns;27ns;20ns;22ns@3V,15pF;18ns | |
| Output Logic Level - Low | 0V;200mV;500mV;650mV | |
| Features | Noise suppression function | |
| Input Logic Level - Low | - | |
| Input Logic Level - High | - | |
| Operating Temperature | -40℃~+125℃ | |
| Number of Circuits | 6 | |
| Output Logic Level - High | 1.2V;1.8V;2.5V;2.8V;4.3V;2.4V;3.6V | |
| Quiescent Current(Iq) | 40uA | |
| Current - Output High(IOH) | - | |
| Number of Channels | - | |
| Current - Output Low(IOL) | - |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LV14 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC14 and 74HCT14. The 74LV14 provides six inverting buffers with Schmitt-trigger input. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage V(T+) and the negative voltage V(T-) is defined as the input hysteresis voltage VH.
Features
- Wide supply voltage range from 1.0 V to 5.5 V
- CMOS low power dissipation
- Optimized for low voltage applications: 1.0 V to 3.6 V
- Accepts TTL input levels between V(CC)=2.7 V and V(CC)=3.6 V
- Typical output ground bounce <0.8 V at V(CC)=3.3 V and T(amb)=25 °C
- Typical HIGH-level output voltage (V(0H)) undershoot: >2 V at V(CC)=3.3 V and T(amb)=25 °C
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.5 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Applications
- Wave and pulse shapers for highly noisy environments
- Astable multivibrators
- Monostable multivibrators
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

