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Nexperia 74LV00BQ,115
| Manufacturer | |
| MPN | 74LV00BQ,115 |
| LCSC Part # | C547850 |
| Packaging | DHVQFN-14-EP(2.5x3) |
| Customer # | |
| Key Attributes | 40uA 1V~5.5V 14ns@5V,50pF DHVQFN-14-EP(2.5x3) Gates and Inverters RoHS |
| Datasheet |  Nexperia 74LV00BQ,115 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-14-EP(2.5x3) | |
| Features | Overvoltage-tolerant input | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - Low | 300mV;600mV;800mV | |
| Input Logic Level - High | 900mV;1.4V;2V | |
| Logic Family | 74LV | |
| Output Logic Level - High | 1.8V;2.4V;2.5V;3.6V | |
| Quiescent Current(Iq) | 40uA | |
| Voltage - Supply | 1V~5.5V | |
| Current - Output High(IOH) | 12mA | |
| Number of Channels | 4;2 | |
| Propagation Delay | 14ns@5V,50pF | |
| Output Logic Level - Low | 200mV;500mV;650mV | |
| Current - Output Low(IOL) | 12mA |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
The 74LV00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.
Features
AI Translation
- Wide supply voltage range from 1.0 to 5.5 V
- CMOS low power dissipation
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Optimized for low voltage applications: 1.0 V to 3.6 V
- Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
- Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
- Typical HIGH-level output voltage (V₀H) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
- Complies with JEDEC standards:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.5 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Applications
AI Translation
- Low-voltage applications
- TTL input level compatible
- Logic gate circuits in electronic equipment
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 0.3654 | $ 0.37 |
| 200+ | $ 0.1414 | $ 28.28 |
| 500+ | $ 0.1365 | $ 68.25 |
| 1,000+ | $ 0.134 | $ 134.00 |
Standard Packaging3000/Full Reel | ||
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | DHVQFN-14-EP(2.5x3) | |
| Features | Overvoltage-tolerant input | |
| Operating Temperature | -40℃~+125℃ | |
| Input Logic Level - Low | 300mV;600mV;800mV | |
| Input Logic Level - High | 900mV;1.4V;2V | |
| Logic Family | 74LV | |
| Output Logic Level - High | 1.8V;2.4V;2.5V;3.6V | |
| Quiescent Current(Iq) | 40uA | |
| Voltage - Supply | 1V~5.5V | |
| Current - Output High(IOH) | 12mA | |
| Number of Channels | 4;2 | |
| Propagation Delay | 14ns@5V,50pF | |
| Output Logic Level - Low | 200mV;500mV;650mV | |
| Current - Output Low(IOL) | 12mA |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
The 74LV00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.
Features
AI Translation
- Wide supply voltage range from 1.0 to 5.5 V
- CMOS low power dissipation
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Optimized for low voltage applications: 1.0 V to 3.6 V
- Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
- Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
- Typical HIGH-level output voltage (V₀H) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
- Complies with JEDEC standards:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C (2.7 V to 3.6 V)
- JESD36 (4.5 V to 5.5 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Applications
AI Translation
- Low-voltage applications
- TTL input level compatible
- Logic gate circuits in electronic equipment
C547850 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |