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Nexperia 74AUP2G132DC,125
| Manufacturer | |
| MPN | 74AUP2G132DC,125 |
| LCSC Part # | C546071 |
| Packaging | VSSOP-8-0.5mm |
| Customer # | |
| Key Attributes | Low-power dual 2-input NAND Schmitt trigger |
| Datasheet |  Nexperia 74AUP2G132DC,125 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | VSSOP-8-0.5mm | |
| Input Logic Level - High | - | |
| Input Logic Level - Low | - | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Operating Temperature | -40℃~+125℃ | |
| Logic Family | 74AUP | |
| Output Logic Level - High | 2.6V | |
| Quiescent Current(Iq) | 500nA | |
| Voltage - Supply | 800mV~3.6V | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 4mA | |
| Propagation Delay | 7.8ns@3.6V,30pF | |
| Output Logic Level - Low | 440mV | |
| Current - Output Low(IOL) | 4mA |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using lOFF. The lOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
AI Translation
- Wide supply voltage range from 0.8 V to 3.6 V
- CMOS low power dissipation
- High noise immunity
- Low static power consumption; lCC = 0.9 μA (maximum)
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Overvoltage tolerant inputs to 3.6 V
- Low noise overshoot and undershoot < 10 % of VCC
- IOFF circuitry provides partial Power-down mode operation
- Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V), JESD8-11 (0.9 V to 1.65 V), JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Applications
AI Translation
- Wave and pulse shaper
- Astable multivibrator
- Monostable multivibrator
In-Stock: 5,661
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.5441 | $ 0.54 |
| 10+ | $ 0.4389 | $ 4.39 |
| 30+ | $ 0.3871 | $ 11.61 |
| 100+ | $ 0.3352 | $ 33.52 |
| 500+ | $ 0.3029 | $ 151.45 |
| 1,000+ | $ 0.2867 | $ 286.70 |
Standard Packaging3000/Full Reel | ||
Better price for more quantity?
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | Nexperia | |
| Packaging | VSSOP-8-0.5mm | |
| Input Logic Level - High | - | |
| Input Logic Level - Low | - | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Operating Temperature | -40℃~+125℃ | |
| Logic Family | 74AUP | |
| Output Logic Level - High | 2.6V | |
| Quiescent Current(Iq) | 500nA | |
| Voltage - Supply | 800mV~3.6V | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 4mA | |
| Propagation Delay | 7.8ns@3.6V,30pF | |
| Output Logic Level - Low | 440mV | |
| Current - Output Low(IOL) | 4mA |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
AI Translation
The 74AUP2G132 is a dual 2-input NAND gate with Schmitt-trigger inputs. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using lOFF. The lOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
AI Translation
- Wide supply voltage range from 0.8 V to 3.6 V
- CMOS low power dissipation
- High noise immunity
- Low static power consumption; lCC = 0.9 μA (maximum)
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Overvoltage tolerant inputs to 3.6 V
- Low noise overshoot and undershoot < 10 % of VCC
- IOFF circuitry provides partial Power-down mode operation
- Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V), JESD8-11 (0.9 V to 1.65 V), JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V)
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Applications
AI Translation
- Wave and pulse shaper
- Astable multivibrator
- Monostable multivibrator
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |