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Nexperia 74AUP1G97GM,115
| Manufacturer | |
| MPN | 74AUP1G97GM,115 |
| LCSC Part # | C545921 |
| Packaging | XSON-6(1x1.5) |
| Customer # | |
| Key Attributes | Low-power configurable multiple function gate |
| Datasheet |  Nexperia 74AUP1G97GM,115 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters - Multi-Function, Configurable | |
| Manufacturer | Nexperia | |
| Packaging | XSON-6(1x1.5) | |
| Logic Family | 74AUP Series | |
| Propagation Delay | 3.9ns@3V,5pF | |
| Voltage - Supply | 800mV~3.6V | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - Low | 440mV | |
| Input Logic Level - Low | - | |
| Input Logic Level - High | - | |
| Current - Output Low(IOL) | 4mA | |
| Output Logic Level - High | 2.6V | |
| Quiescent Current(Iq) | 900nA | |
| Current - Output High(IOH) | 4mA | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Number of Channels | 1 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 5000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74AUP1G97 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 0.8 V to 3.6 V
- CMOS low power dissipation
- High noise immunity
- Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V)
- Low static power consumption; ICC = 0.9 μA (maximum)
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Overvoltage tolerant inputs to 3.6 V
- Low noise overshoot and undershoot < 10 % of VCC
- IOFF circuitry provides partial Power-down mode operation
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 5+ | $ 0.3101 | $ 1.55 |
| 50+ | $ 0.2632 | $ 13.16 |
| 150+ | $ 0.2431 | $ 36.47 |
| 500+ | $ 0.218 | $ 109.00 |
| 2,500+ | $ 0.2068 | $ 517.00 |
| 5,000+ | $ 0.2001 | $ 1000.50 |
Standard Packaging5000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters - Multi-Function, Configurable | |
| Manufacturer | Nexperia | |
| Packaging | XSON-6(1x1.5) | |
| Logic Family | 74AUP Series | |
| Propagation Delay | 3.9ns@3V,5pF | |
| Voltage - Supply | 800mV~3.6V | |
| Operating Temperature | -40℃~+125℃ | |
| Output Logic Level - Low | 440mV | |
| Input Logic Level - Low | - | |
| Input Logic Level - High | - | |
| Current - Output Low(IOL) | 4mA | |
| Output Logic Level - High | 2.6V | |
| Quiescent Current(Iq) | 900nA | |
| Current - Output High(IOH) | 4mA | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Number of Channels | 1 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 5 |
| Multiple | 5 |
| Standard Packaging | 5000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74AUP1G97 is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features
- Wide supply voltage range from 0.8 V to 3.6 V
- CMOS low power dissipation
- High noise immunity
- Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V)
- Low static power consumption; ICC = 0.9 μA (maximum)
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Overvoltage tolerant inputs to 3.6 V
- Low noise overshoot and undershoot < 10 % of VCC
- IOFF circuitry provides partial Power-down mode operation
- ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
- Multiple package options
- Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |