XBLW SN74LS595DTR(XBLW)

The SN74LS595 is an 8-bit serial-in, serial or parallel-out shift register with storage register and 3-state outputs. The shift register and storage register have separate clocks. The device features a serial input (DS) and serial output (Q7S) for cascading, and an asynchronous reset MR input. A low on MR resets the shift register. Data is shifted on the low-to-high transition of the SHCP input. Data in the shift register is transferred to the storage register on the low-to-high transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. When the output enable input (OE) is low, the data in the storage register appears at the outputs. A high on OE causes the outputs to assume a high-impedance state. Operation of the OE input does not affect the state of the registers. The inputs include clamp diodes, which allow the use of current-limiting resistors to interface inputs to voltages higher than VCC.

• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• Operating temperature range: -20°C to +85°C
• Package: DIP-16/SOP-16/TSSOP-16