TI TMS320C5517AZCH20

This device is specifically designed for applications requiring low operating and standby power consumption. It is based on the CPU processor core generated by the TMS320C55x DSP. The C55x DSP architecture achieves high performance and low power consumption through increased parallelism and an emphasis on energy conservation.

The CPU supports an internal bus structure, which includes one program bus, one 32-bit read bus, two 16-bit data read buses, two data write buses, and additional buses dedicated to peripheral and DMA operations. It can execute up to four 16-bit data reads and two 16-bit data writes in a single cycle.

It also includes four DMA controllers, each with 4 channels, providing 16 independent channels for data transfer without CPU intervention. Each DMA controller can perform a 32-bit data transfer per cycle, running in parallel with and independent of the CPU.

The C55x CPU provides two multiply-accumulate (MAC) units, each capable of performing a 17-bit by 17-bit multiplication and a 32-bit addition in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. The use of the ALU is controlled by the instruction set to optimize parallel operation and power consumption.

The address unit (AU) and data unit (DU) within the C55x CPU manage these resources. The C55x CPU supports a variable byte-width instruction set to improve code density. The instruction unit (IU) fetches 32-bit instructions from internal or external memory and queues them for the program unit (PU). The PU decodes the instructions, directs tasks to the address unit and data unit resources, and manages the fully protected pipeline. The branch prediction function avoids pipeline flushing during conditional instruction execution.

The GPIO function, along with the 10-bit SAR ADC, provides sufficient pins for status, interrupts, and bit I/O for keyboard and media interfaces. Serial media is supported by the following devices: two multimedia card and secure digital (MMC and SD) peripherals, three internal inter-IC sound (I2S bus) modules, one serial port interface (SPI) with four-chip select, one multi-channel buffered serial port interface (McSPI) with three-chip select master and slave, one multi-channel serial port (McBSP), one I2C multi-master and slave interface, and one universal asynchronous receiver/transmitter (UART) interface.

The device's peripheral set includes an external memory interface (EMIF), which provides seamless access to asynchronous memories such as EPROM, NOR, NAND, and SRAM, as well as high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Other peripherals include: a configurable 16-bit universal host port interface (UHPI), a high-speed universal serial bus (USB 2.0) supporting only device mode, a real-time clock (RTC), three general-purpose timers (one of which can be configured as a watchdog timer), and an analog phase-locked loop (APLL) clock generator.

The device also contains a tightly coupled FFT hardware accelerator - supporting 8 to 1024-point (powers of 2) real and complex FFTs, and three integrated low-dropout regulators (LDOs) - powering various parts of the device (except for CVDDRTC, which requires an external power supply): the ANA_LDO provides 1.3V for the SAR and power management circuit (VDDA_ANA), the DSP_LDO provides 1.3V or 1.05V for the DSP core (CVDD) (which can be selected in real-time by software once the operating frequency range is detected), and the USB_LDO provides 1.3V for the USB core digital circuit (USB_VDD1P3) and PHY circuit (USB_VDDA1P3).

• Core:
  • High-performance, low-power TMS320C55x fixed-point DSP
  • 13.33ns to 5ns instruction cycle time
  • 75MHz to 200MHz clock rate
  • One or two instructions executed per cycle
  • Two multiply-accumulate units (up to 450 MMACS)
  • Two ALUs
  • Three internal data/operand read buses and two write buses
  • Software-compatible with C55x devices
  • Industrial temperature devices available
• 320KB zero-wait-state on-chip RAM:
  • 64KB dual-access RAM (DARAM), 8 blocks of 4K × 16-bit
  • 256KB single-access RAM (SARAM), 32 blocks of 4K × 16-bit
• 128KB zero-wait-state on-chip ROM (4 blocks of 16K × 16-bit)
• Tightly coupled FFT hardware accelerator
• DMA controller: four DMAs, each with four channels
• Three 32-bit GP timers: one selectable as watchdog or GP timer option, with external GPIO clock input
• Two multimedia card and secure digital (eMMC, MMC, and SD) interfaces
• SPI with four chip selects
• Master and slave I2C bus
• Three I2S bus modules for data transfer
• 10-bit 4-input successive approximation (SAR) ADC
• IEEE 1149.1 (JTAG) boundary-scan compatible
• Up to 26 GPIO pins (multiplexed with other functions)
• Power:
  • Four core-isolated power domains: analog, RTC, CPU and peripherals, and USB
  • Four I/O-isolated power domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO
  • 1.05V core, 1.8V / 2.75V / 3.3V I/O
  • 1.3V core, 1.8V / 2.75V / 3.3V I/O
  • 1.4V core, 1.8V / 2.75V / 3.3V I/O
• Clocking:
  • RTC with crystal oscillator input, independent clock domain and power supply
  • Software-programmable PLL clock generator
• Boot loader:
  • On-chip ROM boot loader
  • Unencrypted boot supported on each peripheral
• Package: 196-terminal lead-free plastic BGA package (suffix ZCH), 0.65mm pitch

• Digital two-way radio
• Low-power analytics applications (e.g., voice recognition, vision sensing, and fingerprint recognition)
• Voice applications (e.g., voice recorders, hands-free kits, and voice enhancement subsystems)
• Audio devices (e.g., echo-canceling headsets and speakerphones, or wireless headsets and microphones)
• Portable medical devices