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TI PCM5100APWRoHS

Manufacturer
MPN
PCM5100APW
LCSC Part #
C544856
Packaging
TSSOP-20
Customer #
Key Attributes
Audio stereo DAC with PLL and 32-bit, 384kHz PCM interface
Datasheetpdf iconTI PCM5100APW
In-Stock: 99
99 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 3.4928$ 3.49
10+$ 3.008$ 30.08
30+$ 2.7047$ 81.14
70+$ 2.181$ 152.67
490+$ 2.0399$ 999.55
1,400+$ 1.9799$ 2771.86
Standard Packaging70/Full Tube
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Data Acquisition/ADCs/DACs - Special Purpose
ManufacturerTI
PackagingTSSOP-20
FeaturesDigital filtering;Power-down mode
Voltage Reference Drift-
Data Rate-
Voltage Reference Value-
Number of Channels2
Operating Temperature-25℃~+85℃
InterfaceI2S
ChipType-
Voltage - Supply1.8V~3.6V
Quiescent Current0.8mA
Integral non - linearity-
Voltage Reference-
Resolution (Bits)32;-

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging70
Sales UnitPiece

Introduction

AI Translation

The PCM510xA devices are a family of monolithic CMOS ICs consisting of stereo DACs and additional support circuitry in a TSSOP package. The PCM510xA devices utilize TI's latest generation advanced segmented DAC architecture to achieve excellent dynamic performance and enhanced tolerance to clock jitter. With DirectPath charge pump technology, the PCM510xA devices provide a 2.1 VRMS ground-centered output — eliminating the need for DC-blocking capacitors at the output and the external muting circuitry traditionally associated with single-supply line drivers. The integrated line driver supports loads as low as 1 kΩ per pin, surpassing all other charge pump-based line drivers in performance. The on-chip PLL eliminates the need for a system clock (commonly referred to as a master clock), enabling a 3-wire I2C connection and reducing system EMI. Intelligent clock error detection and PowerSense undervoltage protection form a dual-layer system that eliminates clicks and pops.

Features

AI Translation
  • Ultra-low out-of-band noise
  • High-performance integrated audio PLL with BCK reference, generates SCK internally
  • Direct line-level 2.1 VRMS output
  • No DC-blocking capacitors required
  • Line-level output supports loads as low as 1kΩ
  • Intelligent muting system; soft ramp-up/ramp-down with analog mute for 120dB mute SNR
  • Accepts 16-, 24-, and 32-bit audio data
  • PCM data formats: I2S, left-justified
  • Automatic power-saving mode when LRCK and BCK are deasserted
  • 1.8V or 3.3V fail-safe LVCMOS digital inputs
  • Simple configuration via hardware pins
  • Single supply: 3.3V analog supply, 1.8V or 3.3V digital supply
  • AEC-Q100 compliant

Applications

AI Translation
  • A/V receivers, DVD, BD players
  • Automotive infotainment systems and telematics
  • HDTV receivers
  • Automotive aftermarket amplifiers