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TI SN74ABT827PW
| Manufacturer | |
| MPN | SN74ABT827PW |
| LCSC Part # | C544762 |
| Packaging | TSSOP-24 |
| Customer # | |
| Key Attributes | 10-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| Datasheet |  TI SN74ABT827PW |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | TSSOP-24 | |
| Input type | - | |
| Voltage - Supply | 4.5V~5.5V | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 32mA | |
| Series | 74ABT | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 64mA | |
| Number of Bits per Element | 10 | |
| Channel Type | Unidirectional | |
| Features | Power-off isolation;Output enable | |
| Number of Elements | 1 | |
| Quiescent Current | 250uA | |
| Propagation Delay | 2.6ns@5V,50pF |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 60 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The ’ABT827 provides true data at the outputs.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Features
- State-of-the-Art EPIC-ΙΙB BiCMOS Design
- Significantly Reduces Power Dissipation
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical vOLP (Output Ground Bounce) < 1 V at Vcc = 5 V, TA = 25℃
- High-Impedance State During Power Up and Power Down
- High-Drive Outputs (-32 mA I0H, 64 mA I0L)
- Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 1.3817 | $ 1.38 |
| 10+ | $ 1.3496 | $ 13.50 |
| 30+ | $ 1.3272 | $ 39.82 |
| 100+ | $ 1.3047 | $ 130.47 |
Standard Packaging60/Full Tube | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | TSSOP-24 | |
| Input type | - | |
| Voltage - Supply | 4.5V~5.5V | |
| Output Type | Tri-State | |
| Current - Output High(IOH) | 32mA | |
| Series | 74ABT | |
| Operating Temperature | -40℃~+85℃ | |
| Current - Output Low(IOL) | 64mA | |
| Number of Bits per Element | 10 | |
| Channel Type | Unidirectional | |
| Features | Power-off isolation;Output enable | |
| Number of Elements | 1 | |
| Quiescent Current | 250uA | |
| Propagation Delay | 2.6ns@5V,50pF |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 60 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The ’ABT827 provides true data at the outputs.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Features
- State-of-the-Art EPIC-ΙΙB BiCMOS Design
- Significantly Reduces Power Dissipation
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical vOLP (Output Ground Bounce) < 1 V at Vcc = 5 V, TA = 25℃
- High-Impedance State During Power Up and Power Down
- High-Drive Outputs (-32 mA I0H, 64 mA I0L)
- Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |