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TI TMS320DM8127SCYE3 product image
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TI TMS320DM8127SCYE3RoHS

Manufacturer
TI
MPN
TMS320DM8127SCYE3
LCSC Part #
C544687
Packaging
FCBGA-684
Customer #
Key Attributes
DaVinci Video Processors
Datasheetpdf iconTI TMS320DM8127SCYE3

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/DSP (Digital Signal Processors)
ManufacturerTI
PackagingFCBGA-684
CPU CoreOthers
Maximum Speed750MHz;1GHz
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging60
Sales UnitPiece

Features

AI Translation
  • High-Performance DaVinci Video Processors Up to 1-GHz ARM Cortex-A8 RISC Core Up to 750-MHz C674x VLIW DSP – Up to 6000 MIPS and 4500 MFLOPS – Fully Software-Compatible with C6Zx+ , G64x+
  • ARM Cortex-A8 Core – ARMv7 Architecture • In-Order, Dual-Issue, Superscalar Processor Core • Neon Multimedia Architecture • Supports Integer and Floating Point • Jazelle RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture – 32KB of Instruction and Data Caches – 256KB of L2 Cache – 64KB of RAM, 48KB of Boot ROM
  • TMS320C674x Floating-Point VLIW DSP – 64 General-Purpose Registers (32-Bit) – Six ALU (32-/40-Bit) Functional Units • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point • Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks • Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal or Square Root Operations Per Cycle – Two Multiply Functional Units • Mixed-Precision IEEE Floating-Point Multiply Supported up to: - 2 SPxSP→SP Per Clock - 2 SPxSP→DP Every Two Clocks - 2 SPxDP→DP Every Three Clocks - 2 DPxDP→DP Every Four Clocks • Fixed-Point Multiply Supports Two 32x32 Multiplies, Four 16x16 -Bit Multiplies Including Complex Multiplies, or Eight 8x8 -Bit Multiplies per Clock Cycle
  • 128KB of On-Chip Memory Controller (OCMC) RAM
  • Imaging Subsystem (ISS) – Camera Sensor Connection • Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8- and 16-Bit) • CSI2 Serial Connection – Image Sensor Interface (ISIF) for Handling Image and Video Data From the Camera Sensor – Image Pipe Interface (IPIPEIF) for Image and Video Data Connection Between Camera Sensor, ISIF, IPIPE, and DRAM – Image Pipe (IPIPE) for Real-Time Image and Video Processing – Resizer • Resizing Image and Video From 1/16x to 8x • Generating Two Different Resizing Outputs Concurrently – Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) Control
  • Face Detect Engine (FD) – Hardware Face Detection for up to 35 Faces at OPP100
  • Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine – Encode, Decode, Transcode Operations – H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG
  • Media Controller – Controls the HDVPSS and ISS
  • Endianness – ARM and DSP Instructions/Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS) – One 165-MHz HD Video Capture Input • One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD Capture Ports – Two 165-MHz HD Video Display Outputs • One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output – Composite or S-Video Analog Output – Macrovision Support Available – Digital HDMI 1.3 Transmitter With Integrated PHY – Advanced Video Processing Features Such as Scan, Format, Rate Conversion – Three Graphics Layers and Compositors
  • Dual 32-Bit DDR2/DDR3 SDRAM Interfaces – Supports up to DDR2-800 and DDR3-1066 – Up to Eight x 8 Devices Total 2GB of Total Address Space – Dynamic Memory Manager (DMM)
  • Programmable Multi-Zone Memory Mapping and Interleaving • Enables Efficient 2D Block Accesses • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring • Optimizes Interlaced Accesses
  • General-Purpose Memory Controller (GPMC) – 8- or 16-Bit Multiplexed Address and Data Bus – 512MB of Address Space Divided Among up to 8 Chip Selects – Glueless Interface to NOR Flash, NAND Flash (BCH/Hamming Error Code Detection), SRAM and Pseudo-SRAM – Error Locator Module (ELM) Outside of GPMC to Provide Up to 16-Bit or 512-Byte Hardware ECC for NAND – Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs, and so Forth
  • Enhanced Direct Memory Access (EDMA) Controller – Four Transfer Controllers – 64 Independent DMA Channels and 8 Independent QDMA Channels
  • Dual Port Ethernet (10/100/1000 Mbps) With Optional Switch – IEEE 802.3 Compliant (3.3-V I/O Only) – MII/RMII/GMII/RGMII Media Independent Interfaces – Management Data I/O (MDIO) Module – Reset Isolation – IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet Protocols
  • Dual USB 2.0 Ports With Integrated PHYs – USB2.0 High- and Full-Speed Clients – USB2.0 High-, Full-, and Low-Speed Hosts, or OTG – Supports End Points 0–15
  • One PCI Express 2.0 Port With Integrated PHY – Single Port With One Lane at 5.0 GT/s – Configurable as Root Complex or Endpoint
  • Eight 32-Bit General-Purpose Timers (Timer1–8)
  • One System Watchdog Timer (WDT0)
  • Six Configurable UART/IrDA/CIR Modules – UART0 With Modem Control Signals – Supports up to 3.6864 Mbps UART0/1/2 – Supports up to 12 Mbps UART3/4/5 – SIR, MIR, FIR (4.0 MBAUD), and CIR
  • Four Serial Peripheral Interfaces (SPIs) (up to 48 MHz) – Each With Four Chip Selects
  • Three MMC/SD/SDIO Serial Interfaces (up to 48 MHz) – Three Supporting up to 1-, 4-, or 8-Bit Modes
  • Four Inter-Integrated Circuit (I²C Bus) Ports
  • Six Multichannel Audio Serial Ports (McASPs) – Dual Ten Serializer Transmit and Receive Ports – Quad Four Serializer Transmit and Receive Ports – DIT-Capable For S/PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP) – Transmit and Receive Clocks up to 48 MHz – Two Clock Zones and Two Serial Data Pins – Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC) – One-Time or Periodic Interrupt Generation
  • Up to 128 General-Purpose I/O (GPIO) Pins
  • One Spin Lock Module with up to 128 Hardware Semaphores
  • One Mailbox Module with 12 Mailboxes
  • On-Chip ARM ROM Bootloader (RBL)
In-Stock: 7
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QtyUnit PriceTotal Amount
1+$ 92.0449$ 92.04
30+$ 87.5214$ 2625.64
Standard Packaging60/Full Tray
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