Pangomicro PGL25G-6IMBG324

The Logos series programmable logic devices are a new generation of low-power, low-cost FPGAs featuring a fully proprietary architecture and mainstream 40nm process technology. They incorporate innovative Configurable Logic Modules (CLM), dedicated 18Kb block memory (DRM), Arithmetic Processing Modules (APM), versatile high-performance IOs, and rich on-chip clock resources. The devices also integrate hard IP cores including a Memory Controller (HMEMC) and Analog-to-Digital Conversion module (ADC), support multiple configuration modes, and provide bitstream encryption and Device ID (UID) features to protect user design security. These devices are well-suited for a wide range of applications including video, industrial control, automotive electronics, and consumer electronics.

• Low cost, low power consumption
• Low-power, mature 40nm CMOS process
• Core voltage as low as 1.1V
• Multi-standard IO support
• Up to 308 user IOs, supporting 1.2V, 1.5V, 1.8V, 2.5V, 3.3V IO standards
• HSTL, SSTL memory interface standard support
• MIPI D-PHY interface standard support
• Differential standards support: LVDS, MINI-LVDS, SUB-LVDS, SLVS (MIPI 2-wire level standard), TMDS (for HDMI, DVI interfaces)
• Programmable IO BUFFER with high-performance IOLOGIC
• Flexible programmable logic module CLM
• LUT5 logic structure: each CLM contains 4 multi-function LUT5s and 6 registers
• Fast arithmetic carry logic support
• Distributed RAM mode support
• Cascade chain support
• DRM with multiple read/write modes
• Single DRM provides 18Kb storage, configurable as 2 independent 9Kb blocks
• Multiple operating modes: single-port (SP) RAM, dual-port (DP) RAM, simple dual-port (SDP) RAM, ROM, and FIFO
• Dual-port RAM and SDP RAM support mixed data width on both ports
• Normal-Write, Transparent-Write, and Read-before-Write modes support
• Byte-Write support
• High-efficiency arithmetic processing unit APM
• Each APM supports one 18×18 or two 9×9 operations
• Input/output register support
• 48-bit accumulator support
• Signed and Unsigned arithmetic support
• Integrated hard-core memory controller HMEMC
• DDR2, DDR3, LPDDR support
• Single HMEMC supports X8/X16 data width
• Standard AXI4 bus protocol support
• DDR3 write leveling and DQS gate training support
• DDR3 maximum rate up to 800Mbps
• Integrated ADC hard core
• 10-bit resolution, 1MSPS sampling rate (standalone ADC operation)
• Up to 12 input channels
• Integrated temperature sensor
• Rich clock resources
• 3 types of clock networks, flexibly configurable
• Region-based global clock network
• 4 regional clocks per region with vertical cascade support
• High-speed IO clock with IO clock division support
• Optional data address latch and output register
• Multiple integrated PLLs, each supporting up to 5 clock outputs
• Flexible configuration options
• Multiple programming modes supported
• JTAG mode compliant with IEEE 1149 and IEEE 1532 standards
• Master SPI supports up to 8-bit data width for improved programming speed
• BPI X8/X16, Serial Slave, and Parallel Slave mode support
• AES-256 bitstream encryption support(2), 64-bit UID protection
• SEU error detection and correction support
• Multi-version bitstream fallback support
• Watchdog timeout detection support
• Programming download support
• Online debug support

• Video
• Industrial Control
• Automotive Electronics
• Consumer Electronics