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NXP FS32V234CTN2VUB product image
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NXP FS32V234CTN2VUBRoHS

Manufacturer
NXP
MPN
FS32V234CTN2VUB
LCSC Part #
C5364356
Packaging
FCPBGA-621(17x17)
Customer #
Key Attributes
1GHz FCPBGA-621(17x17) Microprocessors RoHS
Datasheetpdf iconNXP FS32V234CTN2VUB

Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microprocessors
ManufacturerNXP
PackagingFCPBGA-621(17x17)
CPU Core-
CPU Maximum Speed1GHz
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging1000
Sales UnitPiece

Features

AI Translation
  • ARM Cortex - A53, 64 - bit CPU
    • Up to 1000 MHz Quad ARM Cortex - A53
    • 32 KB/32 KB I - /D - L1 Cache
    • NEON MPE co - processor
    • Dual precision FPU
    • 2 clusters with 2 CPUs and 256 KB L2 cache each
    • Memory Management Unit GIC Interrupt Controller ECC/parity error support for its memories
    • Generic timers
    • Fault encapsulation by hardware for redundant executed application software on multiple core cluster
  • ARM Cortex - M4, 32 - bit CPU
    • Up to 133 MHz 16 KB/16 KB I - /D - L1 Cache
    • 32 + 32 KB tightly coupled memory (TCM) ECC/parity support for its memories
  • Clocks
    • Phase Locked Loops (PLLs)
    • 1 external crystal oscillator (FXOSC)
    • 1 FIRC oscillator
  • System protection and power management features
    • Flexible run modes to consume low power based on application needs
    • Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents
    • Power gating of unused A53 cores and GPU
    • Low and high voltage warning and detect
    • Hardware CRC module to support fast cyclic redundancy checks (CRC)
    • 120 - bit unique chip identifier
    • Hardware watchdog
  • eDMA controller with 32 channels (with DMAMUX)
    • Extended Resource Domain Controller
  • Safety concept
    • ISO 26262, ASIL level target
    • Measures to detect faults in memory and logic
    • Measures to detect single point and latent faults
    • Quantitative out of context analysis of functional safety (FMEDA) tailored to application specifics
    • Safety manual and FMEDA report available
  • Security
    • CSE with 16 KB of on - chip Secure RAM and ROM.
    • ARM TrustZone (TZ) architecture support
    • Boot from NOR flash with AES - 128 (CTR)
    • On - Chip One - Time Programmable element Controller (OCOTP_CTRL) with on chip electrical fuse array.
    • System JTAG Controller (SJC)
  • Debug functionality
    • Standard JTAG and Compact JTAG
    • 16 - bit Trace port, Serial Wire Output port
  • Timers
    • General purpose timers (FTM)
    • Two Periodic Interrupt Timer (PIT)
    • IEEE 1588 Timers (part of Ethernet Subsystem)
  • Analog
    • 1x 12 - bit 1.8 V SAR ADC with self - test
  • Communications
    • UART(w/ LIN2.1l)
    • Serial peripheral interface (SPI)
    • I2C blocks
    • PCI express 2.0 with endpoint and root complex support
    • LFAST serial link
    • 1 GBit Ethernet with PTP IEEE 1588
    • FD - CAN
    • FlexRay Dual Channel, Version 2.1 RevA
  • Memory interfaces
    • 32 - bit DRAM Controller with support for LPDDR2/DDR3/DDR3L
    • Data rate of up to 1066 MT/s at 533 MHz clock frequency with ECC (SEC - DED - TED) triple error detection support for subregion
    • QuadSPI supporting Execute - In - Place (XIP)
    • Boot flash fault detection and correction using two - dimensional parity.
    • Triple fault detection and single fault correction scheme for external DDR - RAM including address/page fault detection.
  • Video input interfaces, Image processing, graphics processing, display
    • Display Control Unit (2D - ACE) with 24 - bit RGB, GPU frame buffer decoding
    • GPU GC3000 with frame buffer compression
    • 2x VIU (Video interface unit) for camera input
    • 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps)
    • Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions (exposure control, gamma correction)
    • 2x APEX2 - CL Image cognition processor. APEX - 642CL comprises two Array Processing Unit (APU) cores configurable as single SIMD engine with 64 16 - bit Computational Units (CU), or configurable as two core MIMD engines with 32 16 - bit CUs each.
    • CUs are comprised of four Functional Units: 16 - bit Multiplier, Load Store Unit, ALU, and Shifter
    • JPEG video decoder (8/12 - bit)
    • H.264 video decoder (8/10/12 - bit), High - intra and constrained baseline formats
    • H.264 video encode (8/10/12 - bit), High - intra only
    • Fast DMA for data transfers between DRAM and System RAM with CRC
  • Human - Machine Interface (HMI)
    • GPIO pins with interrupt support, DMA request capability, digital glitch filter
    • Configurable slew rate and drive strength on all output pins
  • System RAM
    • 4 MB On - Chip System RAM with ECC
In-Stock: 5
5 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 121.3823$ 121.38
30+$ 115.5741$ 3467.22
Standard Packaging1000/Full Reel
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