- Pinout Diagram
- Footprint Diagram
Images for reference only
EDA ModelsEasyEDA
ST STM32MP135DAE7
| Manufacturer | |
| MPN | STM32MP135DAE7 |
| LCSC Part # | C5360919 |
| Packaging | LFBGA-289(14x14) |
| Customer # | |
| Key Attributes | Arm Cortex-A7 up to 1 GHz, LCD-TFT, camera interface, 2xETH, 2xCAN FD, 2xADC, 24 timers, audio |
| Datasheet |  ST STM32MP135DAE7 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microprocessors | |
| Manufacturer | ST | |
| Packaging | LFBGA-289(14x14) | |
| CPU Core | ARM Cortex-ASeries |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 119 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Includes ST state-of-the-art patented technology
- Core: 32-bit Arm Cortex - A7, L1 32-Kbyte I / 32-Kbyte D, 128-Kbyte unified level 2 cache, Arm NEON and Arm TrustZone
- Memories: External DDR memory up to 1 Gbyte, up to LPDDR2/LPDDR3 - 1066 16-bit, up to DDR3/DDR3L - 1066 16-bit, 168 Kbytes of internal SRAM (128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain), Dual Quad - SPI memory interface, Flexible external memory controller with up to 16-bit data bus (parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC)
- Security/safety: TrustZone peripherals, 12 x tamper pins including 5 x active tamper, Temperature, voltage, frequency and 32 kHz monitoring
- Reset and power management: 1.71 V to 3.6 V I/Os supply (5 V - tolerant I/Os), POR, PDR, PVD and BOR, On - chip LDOs (USB 1.8 V, 1.1 V), Backup regulator (~0.9 V), Internal temperature sensors, Low - power modes: Sleep, Stop, LPLV - Stop, LPLV - Stop2 and Standby, DDR retention in Standby mode, Controls for PMIC companion chip
- Clock management: Internal oscillators (64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator), External oscillators (8 - 48 MHz HSE oscillator, 32.768 kHz LSE oscillator), 4 x PLLs with fractional mode
- General - purpose input/outputs: Up to 135 secure I/O ports with interrupt capability, Up to 6 wakeup
- Interconnect matrix: 2 bus matrices, 64 - bit Arm AMBA AXI interconnect, up to 266 MHz, 32 - bit Arm AMBA AHB interconnect, up to 209 MHz
- 4 DMA controllers to unload the CPU: 56 physical channels in total, 1 x high - speed general - purpose master direct memory access controller (MDMA), 3 x dual - port DMAs with FIFO and request router capabilities for optimal peripheral management
- Up to 30 communication peripherals: 5 x I²C FM + 1 Mbit/s, SMBus/PMBus, 4 x UART + 4 x USART 12.5 Mbit/s, ISO7816 interface, LIN, IIDA, SPI, 5 x SPI (50 Mbit/s, including 4 with full - duplex I²S audio class accuracy via internal audio PLL or external clock), +2 QUADSP1 + 4 with USART, 2 x SAI (stereo audio: I²S PDM, SPDIF Tx), SPDIF Rx with 4 inputs, 2 x SDMMC up to 8 bits (SD/e - MMCTM/SDIO), 2 x CAN controllers supporting CAN FD protocol, 2 x USB2.0 high - speed Host or 1 x USB2.0 high - speed Host + 1 x USB2.0 high - speed OTG simultaneously, 2 x Ethernet MAC/GMAC IEEE 1588v2 hardware, MII/RMII/RGMII, 8 - to 16 - bit camera interface, 3 Mpix < 30 fps or 5Mpix < 15 fps in color or monochrome with pixel clock < 120 MHz (max freq)
- 6 analog peripherals: 2 x ADCs with 12 - bit max. resolution up to 5 Msps, 1 x temperature sensor, 1 x digital filter for sigma - delta modulator (DFSDM) with 4 channels and 2 filters, Internal or external ADC reference VREF+
- Graphics: LCD - TFT controller, up to 24 - bit // RGB888, up to WXGA (1366 × 768) @60 fps or up to Full HD (1920 × 1080) @ 30 fps, pixel clock up to 90 MHz, two layers (incl. 1 secured) with programmable color LUT
- Up to 24 timers and 2 watchdogs: 2 x 32 - bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, 2 x 16 - bit advanced timers, 10 x 16 - bit general - purpose timers (including 2 basic timers without PWM), 5 x 16 - bit low - power timers, Secure RTC with sub - second accuracy and hardware calendar, 4 Cortex - A7 system timers (secure, non - secure, virtual, hypervisor), 2x independent watchdogs
- Hardware acceleration: ECDSA verification with SCA, HASH (SHA - 1, SHA - 224, SHA - 256, SHA - 384, SHA - 512, SHA - 3), HMAC, 1 x true random number generator (6 triple oscillators), 1 x CRC calculation unit
- Debug mode: Arm CoreSight trace and debug: SWD and JTAG interfaces usable as GPIOs, 4 - Kbyte embedded trace buffer
- 3072 - bit fuses including 96 - bit unique ID, up to 1280 bits available for user
- All packages are ECOPACK2 compliant
In-Stock: 719
719 In stock, ships now
Add to BOM List
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 10.6562 | $ 10.66 |
| 10+ | $ 9.1564 | $ 91.56 |
| 30+ | $ 8.2432 | $ 247.30 |
| 119+ | $ 7.4763 | $ 889.68 |
Standard Packaging119/Full Tray | ||
Better price for more quantity?
$
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microprocessors | |
| Manufacturer | ST | |
| Packaging | LFBGA-289(14x14) | |
| CPU Core | ARM Cortex-ASeries |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 119 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Includes ST state-of-the-art patented technology
- Core: 32-bit Arm Cortex - A7, L1 32-Kbyte I / 32-Kbyte D, 128-Kbyte unified level 2 cache, Arm NEON and Arm TrustZone
- Memories: External DDR memory up to 1 Gbyte, up to LPDDR2/LPDDR3 - 1066 16-bit, up to DDR3/DDR3L - 1066 16-bit, 168 Kbytes of internal SRAM (128 Kbytes of AXI SYSRAM + 32 Kbytes of AHB SRAM and 8 Kbytes of SRAM in Backup domain), Dual Quad - SPI memory interface, Flexible external memory controller with up to 16-bit data bus (parallel interface to connect external ICs and SLC NAND memories with up to 8-bit ECC)
- Security/safety: TrustZone peripherals, 12 x tamper pins including 5 x active tamper, Temperature, voltage, frequency and 32 kHz monitoring
- Reset and power management: 1.71 V to 3.6 V I/Os supply (5 V - tolerant I/Os), POR, PDR, PVD and BOR, On - chip LDOs (USB 1.8 V, 1.1 V), Backup regulator (~0.9 V), Internal temperature sensors, Low - power modes: Sleep, Stop, LPLV - Stop, LPLV - Stop2 and Standby, DDR retention in Standby mode, Controls for PMIC companion chip
- Clock management: Internal oscillators (64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz LSI oscillator), External oscillators (8 - 48 MHz HSE oscillator, 32.768 kHz LSE oscillator), 4 x PLLs with fractional mode
- General - purpose input/outputs: Up to 135 secure I/O ports with interrupt capability, Up to 6 wakeup
- Interconnect matrix: 2 bus matrices, 64 - bit Arm AMBA AXI interconnect, up to 266 MHz, 32 - bit Arm AMBA AHB interconnect, up to 209 MHz
- 4 DMA controllers to unload the CPU: 56 physical channels in total, 1 x high - speed general - purpose master direct memory access controller (MDMA), 3 x dual - port DMAs with FIFO and request router capabilities for optimal peripheral management
- Up to 30 communication peripherals: 5 x I²C FM + 1 Mbit/s, SMBus/PMBus, 4 x UART + 4 x USART 12.5 Mbit/s, ISO7816 interface, LIN, IIDA, SPI, 5 x SPI (50 Mbit/s, including 4 with full - duplex I²S audio class accuracy via internal audio PLL or external clock), +2 QUADSP1 + 4 with USART, 2 x SAI (stereo audio: I²S PDM, SPDIF Tx), SPDIF Rx with 4 inputs, 2 x SDMMC up to 8 bits (SD/e - MMCTM/SDIO), 2 x CAN controllers supporting CAN FD protocol, 2 x USB2.0 high - speed Host or 1 x USB2.0 high - speed Host + 1 x USB2.0 high - speed OTG simultaneously, 2 x Ethernet MAC/GMAC IEEE 1588v2 hardware, MII/RMII/RGMII, 8 - to 16 - bit camera interface, 3 Mpix < 30 fps or 5Mpix < 15 fps in color or monochrome with pixel clock < 120 MHz (max freq)
- 6 analog peripherals: 2 x ADCs with 12 - bit max. resolution up to 5 Msps, 1 x temperature sensor, 1 x digital filter for sigma - delta modulator (DFSDM) with 4 channels and 2 filters, Internal or external ADC reference VREF+
- Graphics: LCD - TFT controller, up to 24 - bit // RGB888, up to WXGA (1366 × 768) @60 fps or up to Full HD (1920 × 1080) @ 30 fps, pixel clock up to 90 MHz, two layers (incl. 1 secured) with programmable color LUT
- Up to 24 timers and 2 watchdogs: 2 x 32 - bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input, 2 x 16 - bit advanced timers, 10 x 16 - bit general - purpose timers (including 2 basic timers without PWM), 5 x 16 - bit low - power timers, Secure RTC with sub - second accuracy and hardware calendar, 4 Cortex - A7 system timers (secure, non - secure, virtual, hypervisor), 2x independent watchdogs
- Hardware acceleration: ECDSA verification with SCA, HASH (SHA - 1, SHA - 224, SHA - 256, SHA - 384, SHA - 512, SHA - 3), HMAC, 1 x true random number generator (6 triple oscillators), 1 x CRC calculation unit
- Debug mode: Arm CoreSight trace and debug: SWD and JTAG interfaces usable as GPIOs, 4 - Kbyte embedded trace buffer
- 3072 - bit fuses including 96 - bit unique ID, up to 1280 bits available for user
- All packages are ECOPACK2 compliant
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991a2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991a2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |