Acelamicro ADLY89297
| Manufacturer | AcelamicroAsian Brands |
| MPN | ADLY89297 |
| LCSC Part # | C53145109 |
| Packaging | QFN-24(4x4) |
| Customer # | |
| Key Attributes | QFN-24(4x4) Delay Lines RoHS |
| Datasheet |  Acelamicro ADLY89297 |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Passives/Inductors, Coils, Chokes/Delay Lines | |
| Manufacturer | Acelamicro | |
| Packaging | QFN-24(4x4) |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This device is a dual-channel variable delay chip operating at data rates from DC to 5Gbps. Each channel provides a delay adjustment range of 1.3ns to 6.1ns, with a minimum step size of approximately 5ps and an integral nonlinearity of approximately 15ps. The chip uses a 3-wire SPI interface (SDATA, SCLK, and SLOAD signals) to configure delay values. Each channel features a 10-bit delay control word, and both channels share a common pair of serial control ports. Multiple devices can be cascaded to achieve larger delay values. The chip is available in a QFN24 package measuring 4×4mm and operates over the industrial temperature range of -40℃ to +85℃.
Features
- Dual-channel programmable delay line
- Serial data interface (SDATA, SCLK, SLOAD)
Applications
- Multi-channel clock synchronization
- Automatic test equipment
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 39.772 | $ 39.77 |
| 30+ | $ 37.8379 | $ 1135.14 |
Standard Packaging1/Full Tray | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Passives/Inductors, Coils, Chokes/Delay Lines | |
| Manufacturer | Acelamicro | |
| Packaging | QFN-24(4x4) |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 1 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This device is a dual-channel variable delay chip operating at data rates from DC to 5Gbps. Each channel provides a delay adjustment range of 1.3ns to 6.1ns, with a minimum step size of approximately 5ps and an integral nonlinearity of approximately 15ps. The chip uses a 3-wire SPI interface (SDATA, SCLK, and SLOAD signals) to configure delay values. Each channel features a 10-bit delay control word, and both channels share a common pair of serial control ports. Multiple devices can be cascaded to achieve larger delay values. The chip is available in a QFN24 package measuring 4×4mm and operates over the industrial temperature range of -40℃ to +85℃.
Features
- Dual-channel programmable delay line
- Serial data interface (SDATA, SCLK, SLOAD)
Applications
- Multi-channel clock synchronization
- Automatic test equipment
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |