JSMSEMI 74HC4094D,653-JSM

The 4094 is an 8-stage serial shift register. Each stage is equipped with a storage latch for strobing data from the serial input to the parallel buffered three-state outputs QP0 through QP7. The parallel outputs can be connected directly to common bus lines. Data is shifted on the rising edge of the clock. When the strobe (STR) input is high, the data in each shift register stage is transferred to the storage register. The data in the storage register appears at the outputs as long as the output enable (OE) signal is high. Two serial outputs (QS1 and QS2) are provided for cascading multiple 4094 devices. On the rising edge of the clock, serial data is available at QS1 for high-speed operation in cascaded systems with fast clock rise times. The same serial data is available at QS2 on the next falling edge of the clock. This is used for cascading 4094 devices when the clock rise time is slow. The recommended operating supply voltage VDD ranges from 3V to 15V (with respect to VSS, typically ground). Unused inputs must be connected to VDD, VSS, or another input.

• Wide supply voltage range: 3V to 15V
• Fully static operation
• 5V, 10V, and 15V parametric ratings available
• Standardized symmetrical output characteristics
• Operating temperature range: -40℃ to +125℃
• Package options: DIP16/SOP16/TSSOP16