JSMSEMI 74HC595PW-Q100,118-JSM

The 74HC/HCT595 series are 8-bit serial-in, serial- or parallel-out shift registers with separate storage registers and 3-state outputs. The shift register and storage register have separate clock inputs. The device features a serial input and a serial output for cascading, as well as an asynchronous master reset input. A LOW on the master reset input resets the shift register. Data is shifted on the rising edge of the shift clock input. Data in the shift register is transferred to the storage register on the rising edge of the storage clock input. If the two clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. When the output enable input is LOW, the data in the storage register appears at the outputs. When the output enable input is HIGH, the outputs are in the high-impedance state. Changes on the output enable input do not affect the register state. Inputs include clamp diodes, allowing the input interface to be connected to voltages higher than VCC through current-limiting resistors.

• Input level: CMOS level for 74HC595; TTL level for 74HCT595
• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• Typical shift frequency: 100 MHz
• Operating temperature range: -40℃ ~ +105℃
• Package types: DIP16, SOP16, TSSOP16