- Pinout
- Footprint
JSMSEMI 74LVC2G74DP,125-JSM
| Manufacturer | JSMSEMIAsian Brands |
| MPN | 74LVC2G74DP,125-JSM |
| LCSC Part # | C53114293 |
| Packaging | TSSOP-8 |
| Customer # | |
| Key Attributes | TSSOP-8 Flip Flops RoHS |
| Datasheet |  JSMSEMI 74LVC2G74DP,125-JSM |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | JSMSEMI | |
| Packaging | TSSOP-8 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G74 is a single positive-edge-triggered D-type flip-flop with individual data, clock, set, and reset inputs, plus complementary Q and Q̄ outputs. Set and reset are asynchronous active-LOW inputs that operate independently of the clock input. Data present at the input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. To ensure predictable operation, the data input must remain stable for one setup time prior to the LOW-to-HIGH clock transition.
Features
- Wide supply voltage range: 1.65V ~ 5.5V
- 5V-tolerant outputs, compatible with 5V logic interface
- ±24mA output drive capability (VCC = 3.0V)
- CMOS low power consumption
- Latch-up performance exceeds 250mA
- Operating temperature range: -40°C ~ +125°C
- Package: TSSOP8/VSSOP8
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.5377 | $ 0.54 |
| 10+ | $ 0.4355 | $ 4.36 |
| 30+ | $ 0.3852 | $ 11.56 |
| 100+ | $ 0.3349 | $ 33.49 |
| 500+ | $ 0.3035 | $ 151.75 |
| 1,000+ | $ 0.2877 | $ 287.70 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | JSMSEMI | |
| Packaging | TSSOP-8 |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
The 74LVC2G74 is a single positive-edge-triggered D-type flip-flop with individual data, clock, set, and reset inputs, plus complementary Q and Q̄ outputs. Set and reset are asynchronous active-LOW inputs that operate independently of the clock input. Data present at the input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. To ensure predictable operation, the data input must remain stable for one setup time prior to the LOW-to-HIGH clock transition.
Features
- Wide supply voltage range: 1.65V ~ 5.5V
- 5V-tolerant outputs, compatible with 5V logic interface
- ±24mA output drive capability (VCC = 3.0V)
- CMOS low power consumption
- Latch-up performance exceeds 250mA
- Operating temperature range: -40°C ~ +125°C
- Package: TSSOP8/VSSOP8
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | - |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |