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TI TVP7002PZPRRoHS

Manufacturer
MPN
TVP7002PZPR
LCSC Part #
C527698
Packaging
HTQFP-100(14x14)
Customer #
Key Attributes
I2C Bridge/Converter HTQFP-100(14x14) Video Processing RoHS
Datasheetpdf iconTI TVP7002PZPR
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QtyUnit Price(Reference Only)Total Amount
1+$ 6.7777$ 6.78
10+$ 5.646$ 56.46
30+$ 4.9561$ 148.68
100+$ 4.3788$ 437.88
Standard Packaging1000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Linear/Video Processing
ManufacturerTI
PackagingHTQFP-100(14x14)
Data Rate-
InterfaceI2C
Voltage - Supply1.8V~2V;3V~3.6V
FeaturesBuilt-in phase-locked loop;Programmable gain amplifier
Operating Temperature0℃~+70℃
TypeBridge/Converter

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging1000
Sales UnitPiece

Introduction

AI Translation

The TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 × 1200) resolution at a 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p. The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer. The TVP7002 also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz. All programming of the device is done via an industry-standard I²C interface, which supports both reading and writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.

Features

AI Translation
  • Analog Channels:
    • –6-dB to 6-dB Analog Gain
    • Analog Input Multiplexers (MUXs)
    • Automatic Video Clamp
    • Three Digitizing Channels, Each With Independently Controllable Clamp, Gain, Offset, and Analog-to-Digital Converter (ADC)
    • Clamping: Selectable Clamping Between Bottom Level and Mid Level
    • Offset: 1024-Step Programmable RGB or YPbPr Offset Control
    • Gain: 8-Bit Programmable Gain Control
    • ADC: 8-/10-Bit 165-/110-MSPS ADC
    • Automatic Level Control (ALC) Circuit
    • Composite Sync: Integrated Sync-on-Green Extraction From Green/Luminance Channel
    • Support for DC- and AC-Coupled Input Signals
    • Supports Component Video Standards 480i, 576i, 480p, 576p, 720p, 1080i, and 1080p
    • Supports PC Graphics Inputs up to UXGA
    • Programmable RGB-to-YCbCr Color Space Conversion
  • Horizontal PLL:
    • Fully Integrated Horizontal PLL for Pixel Clock Generation
    • 12-MHz to 165-MHz Pixel Clock Generation From HSYNC Input
    • Adjustable Horizontal PLL Loop Bandwidth for Minimum Jitter
    • 5-Bit Programmable Subpixel Accurate Positioning of Sampling Phase
  • Output Formatter:
    • Supports 20-bit 4:2:2 Outputs With Embedded Syncs
    • Support for RGB/YCbCr 4:4:4 and YCbCr 4:2:2 Output Modes to Reduce Board Traces
    • Dedicated DATACLK Output With Programmable Output Polarity for Easy Latching of Output Data
  • System:
    • Industry-Standard Normal/Fast I²C Interface With Register Readback Capability
    • Space-Saving 100-Pin TQFP Package
    • Thermally-Enhanced PowerPAD Package for Better Heat Dissipation

Applications

AI Translation
  • LCD TVs/Monitors/Projectors
  • DLP TVs/Projectors
  • PDP TVs/Monitors
  • LCOS TVs/Monitors
  • PCTV Set-Top Boxes
  • Digital Image Processing
  • Video Capture/Video Editing
  • Scan Rate/Image Resolution Converters
  • Video Conferencing
  • Video/Graphics Digitizing Equipment