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EDA ModelsEasyEDA
MICROCHIP A3PE1500-2PQG208I
| Manufacturer | |
| MPN | A3PE1500-2PQG208I |
| LCSC Part # | C5233320 |
| Packaging | MQFP-208(28x28) |
| Customer # | |
| Key Attributes | MQFP-208(28x28) FPGAs (Field Programmable Gate Array) RoHS |
| Datasheet |  MICROCHIP A3PE1500-2PQG208I |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | MICROCHIP | |
| Packaging | MQFP-208(28x28) | |
| Embedded Block RAM | 276480bit | |
| Operating Temperature | -40℃~+100℃ |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 24 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- System gate count from 600K to 3M
- True dual-port SRAM capacity from 108Kbit to 504Kbit
- Up to 620 user I/Os
- 130nm, 7-layer metal (6-layer copper), flash-based CMOS process
- Instant-on support (Grade 0)
- Single-chip solution
- Retains programmed design after power-down
- 1Kbit flash ROM with synchronous interface
- System performance up to 350 MHz
- 3.3 V, 66 MHz 64-bit PCI support
- In-system programming via JTAG (IEEE 1532 compliant) with on-chip 128-bit AES decryption
- FlashLock® for FPGA content security protection
- Low-power core voltage
- 1.5 V system support
- Low-impedance flash switches
- Segmented hierarchical routing and clock architecture
- Ultra-high-speed local and long-line networks
- Enhanced high-speed, very-long-line networks
- High-performance, low-skew global networks
- Architecture supports very high utilization
- 700 Mbps DDR, LVDS-capable I/Os
- 1.5 V, 1.8 V, 2.5 V, and 3.3 V mixed-voltage operation
- I/O voltage selection by bank — up to 8 banks per device
- Single-ended I/O standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V input
- Differential I/O standards: LVPECL, LVDS, B-LVDS, and M-LVDS
- Voltage-referenced I/O standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II
- I/O registers on input, output, and enable paths
- Hot-swap and cold-spare I/O support
- Programmable output slew rate and drive strength
- Programmable input delay
- Schmitt trigger option for single-ended inputs
- Weak pull-up/pull-down
- IEEE 1149.1 (JTAG) boundary scan test support
- Pin-compatible packages across the entire ProASIC®3E family
- Six CCC blocks, each integrating one PLL
- Configurable phase shift, multiply/divide, delay capability, and external feedback
- Wide input frequency range (1.5 MHz to 350 MHz)
- Variable aspect ratio 4,608-bit RAM blocks (×1, ×2, ×4, ×9, and ×18 configurations)
- True dual-port SRAM (except ×18 configuration)
- 24 SRAM and FIFO configurations, synchronous operation up to 350 MHz
- M1 ProASIC3E devices — Cortex-M1 soft-core processor with or without debug capability
Not available now
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | MICROCHIP | |
| Packaging | MQFP-208(28x28) | |
| Embedded Block RAM | 276480bit | |
| Operating Temperature | -40℃~+100℃ |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 24 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- System gate count from 600K to 3M
- True dual-port SRAM capacity from 108Kbit to 504Kbit
- Up to 620 user I/Os
- 130nm, 7-layer metal (6-layer copper), flash-based CMOS process
- Instant-on support (Grade 0)
- Single-chip solution
- Retains programmed design after power-down
- 1Kbit flash ROM with synchronous interface
- System performance up to 350 MHz
- 3.3 V, 66 MHz 64-bit PCI support
- In-system programming via JTAG (IEEE 1532 compliant) with on-chip 128-bit AES decryption
- FlashLock® for FPGA content security protection
- Low-power core voltage
- 1.5 V system support
- Low-impedance flash switches
- Segmented hierarchical routing and clock architecture
- Ultra-high-speed local and long-line networks
- Enhanced high-speed, very-long-line networks
- High-performance, low-skew global networks
- Architecture supports very high utilization
- 700 Mbps DDR, LVDS-capable I/Os
- 1.5 V, 1.8 V, 2.5 V, and 3.3 V mixed-voltage operation
- I/O voltage selection by bank — up to 8 banks per device
- Single-ended I/O standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V input
- Differential I/O standards: LVPECL, LVDS, B-LVDS, and M-LVDS
- Voltage-referenced I/O standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II
- I/O registers on input, output, and enable paths
- Hot-swap and cold-spare I/O support
- Programmable output slew rate and drive strength
- Programmable input delay
- Schmitt trigger option for single-ended inputs
- Weak pull-up/pull-down
- IEEE 1149.1 (JTAG) boundary scan test support
- Pin-compatible packages across the entire ProASIC®3E family
- Six CCC blocks, each integrating one PLL
- Configurable phase shift, multiply/divide, delay capability, and external feedback
- Wide input frequency range (1.5 MHz to 350 MHz)
- Variable aspect ratio 4,608-bit RAM blocks (×1, ×2, ×4, ×9, and ×18 configurations)
- True dual-port SRAM (except ×18 configuration)
- 24 SRAM and FIFO configurations, synchronous operation up to 350 MHz
- M1 ProASIC3E devices — Cortex-M1 soft-core processor with or without debug capability
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | 3A991D |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |