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TI F280039CSPNRoHS

Manufacturer
MPN
F280039CSPN
LCSC Part #
C5218666
Packaging
LQFP-80(12x12)
Customer #
Key Attributes
Real-time microcontroller - Fast serial interface with one transmitter and one receiver
Datasheetpdf iconTI F280039CSPN
In-Stock: 161
161 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 9.5074$ 9.51
10+$ 8.1981$ 81.98
30+$ 7.3991$ 221.97
119+$ 6.729$ 800.75
Standard Packaging119/Full Tray
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microcontrollers
ManufacturerTI
PackagingLQFP-80(12x12)
DAC (Bit)12bit
ADC (Bit)12bit
Operating Temperature-40℃~+125℃
Voltage - Supply1.14V~3.63V
Program Memory TypeFLASH
EEPROM-
Program Storage Size384KB
CPU CoreOthers
Core Size32 Bit
CPU Maximum Speed120MHz
Oscillator TypeBuilt-in+External
Number of I/O39

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging119
Sales UnitPiece

Introduction

AI Translation

The TMS320F28003x (F28003x) is a scalable, ultra-low-latency device series designed to improve the efficiency of power electronics, including but not limited to high power density, high switching frequency, and support for the use of GaN and SiC technologies. These applications include motor drives, appliances, hybrid, electric, and powertrain systems, solar and electric vehicle charging, digital power supplies, body electronics and lighting, and test and measurement. The real-time control subsystem is based on TI's 32-bit C28x DSP core, which can provide 120MHz signal processing performance for floating-point or fixed-point code running from on-chip flash or SRAM. The floating-point unit (FPU), trigonometric function accelerator (TMU), and VCRC (cyclic redundancy check) extended instruction set further enhance the performance of the C28x CPU, thereby accelerating the speed of key common algorithms in real-time control systems. The CLA can offload a large number of common tasks from the main C28x CPU. The CLA is an independent 32-bit floating-point math accelerator that executes in parallel with the CPU. In addition, the CLA has its own dedicated storage resources and can directly access the key peripherals required in typical control systems. Like the main features such as hardware breakpoints and hardware task switching, ANSI C subset support is standard. The F28003x supports up to 384KB (192KW) of flash memory, which is divided into three 128KB (64KW) banks and supports parallel programming and execution. Up to 69KB (34.5KW) of on-chip SRAM can also be used to supplement the flash memory. The real-time firmware update hardware enhancement on the F28003x allows for fast context switching from old firmware to new firmware to minimize application downtime when updating the device firmware. The high-performance analog module is integrated on the F28003x real-time microcontroller (MCU) and is tightly coupled with the processing unit and PWM unit to provide better real-time signal chain performance. All 16 PWM channels support frequency-independent resolution modes, which can control various power stages from three-phase inverters to power factor correction and advanced multi-level power topologies. By adding configurable logic blocks (CLBs), users can add custom logic and integrate FPGA-like functions into the C2000 real-time MCU. Various industry-standard communication ports (such as SPI, SCI, I2C, PMBus, LIN, CAN, and CAN FD) not only support connectivity but also provide multiple pin multiplexing options for excellent signal layout. The fast serial interface (FSI) enables robust communication at up to 200Mbps across isolation boundaries. The C2000 platform has added a host interface controller (HIC), which is a high-throughput interface that allows an external host to directly access the resources of the TMS320F28003x.

Features

AI Translation
  • TMS320C28x 32-bit DSP core (at 120 MHz)
  • IEEE 754 floating-point unit (FPU)
  • Fast integer division support (FINTDIV)
  • Trigonometric math unit (TMU)
  • Nonlinear PID (NLPID) control support
  • CRC engine and instructions (VCRC)
  • Ten hardware breakpoints (including ERAD)
  • Programmable control law accelerator (CLA)
  • 120 MHz IEEE 754 single-precision floating-point instructions executing independently of main CPU
  • 384 KB (192 KW) flash in three independent banks (ECC protected)
  • 69 KB (34.5 KW) RAM (ECC protected)
  • Dual-zone security
  • Secure boot and JTAG lock
  • Two internal 10 MHz oscillators, crystal oscillator, or external clock input
  • Windowed watchdog timer module
  • Missing clock detection circuit
  • Dual clock comparator (DCC)
  • Internal VREG enables single-supply design
  • Brown-out reset (BOR) circuit
  • 6-channel DMA controller
  • 55 individually programmable multiplexed GPIO pins
  • 23 digital inputs on analog pins
  • 2 digital I/O (AGPIO) on analog pins
  • Enhanced peripheral interrupt expansion (ePIE)
  • Multiple low-power mode (LPM) support
  • Embedded real-time analysis and diagnostics (ERAD)
  • Unique identification (UID) number
  • One PMBus interface
  • Two I2C ports
  • One CAN/DCAN bus port
  • One CANFD/MCAN bus port with flexible data rate
  • Two SPI ports
  • Two UART-compatible SCI ports
  • Two UART-compatible LIN interfaces
  • FSI with one transmitter and one receiver (up to 200 Mbps)
  • Three 4 MSPS 12-bit ADCs
  • Up to 23 external channels (including two GPDAC outputs)
  • Four integrated post-processing blocks (PPB) per ADC
  • Four window comparators (CMPSS) with 12-bit reference DAC
  • Digital noise filter
  • Two 12-bit buffered DAC outputs
  • 16 ePWM channels, including 8 with high-resolution capability (150 ps resolution)
  • Integrated dead-band support
  • Integrated hardware trip-zone (TZ)
  • Three enhanced capture (eCAP) modules
  • One of three eCAP modules provides high-resolution capture (HRCAP)
  • Two enhanced quadrature encoder pulse (eQEP) modules supporting CW/CCW operation modes
  • Eight Σ-Δ filter module (SDFM) input channels (two parallel filters per channel)
  • Standard SDFM data filtering
  • Comparator filter for fast action on over/under conditions
  • Embedded pattern generator (EPG)
  • Configurable logic block (CLB)
  • 4 logic blocks
  • Enhanced existing peripheral functionality
  • Position manager solution support
  • Host interface controller (HIC)
  • Internal memory accessible from external host
  • Background CRC (BGCRC)
  • Single-cycle CRC operation on 32-bit data
  • AES accelerator
  • Live firmware update (LFU)
  • Fast context switching from old to new firmware
  • Reduced flash bank erase time
  • Diagnostic features
  • Memory power-on self-test (MPOST)
  • Hardware built-in self-test (HWBIST)
  • Targeted for functional safety compliance
  • Developed for functional safety applications
  • Documentation available for ISO 26262 and IEC 61508 system design
  • System functionality targeted at ASIL D and SIL 3
  • Hardware functionality targeted at ASIL B and SIL 2
  • Safety-related certifications
  • ISO 26262 certification up to ASIL B and SIL 2 by TÜV SÜD planned
  • Package options:
    • 100-pin Low-profile Quad Flatpack (LQFP) [suffix PZ]
    • 80-pin LQFP [suffix PN]
    • 64-pin LQFP [suffix PM]
    • 48-pin LQFP [suffix PT]
  • Temperature options:
    • Still air (ambient temperature TA): -40°C to 125°C
    • Junction temperature (TJ): -40°C to 150°C

Applications

AI Translation
  • Electrical - Building Automation - Factory Automation & Control - Motor Drives - Industrial Power - Grid Infrastructure