TI OMAPL132EZWTA2R

The OMAP-L132 C6000 DSP + ARM processor is a low-power application processor based on the ARM926EJ-S and C674x DSP cores. Compared with other TMS320C6000 platform DSPs, it consumes significantly less power. With this device, OEMs and ODMs can fully leverage the flexibility of the fully integrated hybrid processor solution to quickly bring devices with a robust operating system, rich user interfaces, and high processor performance to the market.

This device features a dual-core architecture (including a high-performance TMS320C674x DSP core and an ARM926EJ-S core), which perfectly combines the advantages of DSP and RISC technologies. The ARM926EJ-S is a 32-bit RISC processor core that can execute 32-bit or 16-bit instructions and process 32-bit, 16-bit, or 8-bit data. The core uses a pipeline structure, allowing all components of the processor and memory system to operate continuously.

The ARM9 core is equipped with coprocessor 15 (CP15), a protection module, and a data and program memory management unit (MMU) with a page table buffer. The ARM9 core has separate 16KB instruction cache and 16KB data cache. Both caches are 4-way set associative with virtual index virtual tag (VIVT). The ARM9 core also includes 8KB of RAM (vector table) and 64KB of ROM. The 32KB direct-mapped cache, the Level 1 data cache (L1D), is a 32KB 2-way set associative cache. The Level 2 program cache (L2P) contains 256KB of storage space, shared by the program space and data space. The L2 memory can be configured as mapped memory, cache, or a combination of both.

Although both the ARM9 and other hosts in the system can access the DSP L2, an additional 128KB of RAM shared memory is provided for other hosts to avoid affecting the DSP performance.

For devices supporting security features, TI's Basic Secure Boot can protect users' intellectual property and prevent external entities from modifying user-developed algorithms. The secure boot process starts from a hardware-based "root of trust" to ensure that the code executes from a known secure location. By default, the JTAG port is locked to prevent emulation and debugging attacks; however, the JTAG port can be enabled during the secure boot process for application development.

The boot module is encrypted when stored in external non-volatile memory (e.g., flash or EEPROM) and is decrypted and verified when loaded during secure boot. The encryption and decryption processes protect the customer's IP, enabling customers to securely set up the system and start the device with known trusted code. Basic Secure Boot uses SHA-1 or SHA-256 and AES-128 to verify the boot image. Additionally, it uses AES-128 for boot image encryption. The secure boot process employs a multi-layer encryption mechanism, which not only protects the boot process but also enables secure upgrades of the boot and application software code.

The device uses a 128-bit device-specific key to protect the customer's key. This 128-bit key is generated by a random number generator certified by NIST-800-22 and is only known to the device. When an update is required, the customer can create a new encrypted image. The device can then obtain the image via an external interface (e.g., Ethernet) and overwrite the existing code.

The peripheral set includes: one 10Mbps/100Mbps Ethernet Media Access Controller (EMAC) with a Management Data Input/Output module (MDIO); one USB2.0 OTG interface; two I2C bus interfaces; one Multi-Channel Audio Serial Port (McASP) with 16 serializers and FIFO buffers; two Multi-Channel Buffered Serial Ports (McBSP) with FIFO buffers; two Serial Peripheral Interfaces (SPI) supporting multiple chip selects; four configurable 64-bit general-purpose timers (one of which can be configured as a watchdog); one configurable 16-bit Host Port Interface (HPI); up to nine groups of General-Purpose Input/Output (GPIO) pins (each group containing 16 pins, each supporting programmable interrupt and event generation modes and multiplexing with other peripherals); three UART interfaces (all supporting RTS and CTS); two Enhanced High-Resolution Pulse Width Modulators (eHRPWM) peripherals; three 32-bit Enhanced Capture (eCAP) module peripherals (configurable as three capture inputs or three APWM outputs); two external memory interfaces (one is an asynchronous SDRAM external memory interface (EMIFA) for slow memory or peripherals, and the other is a high-speed DDR2/mobile DDR controller).

The EMAC provides an efficient interface between the device and the network. It supports 10Base-T and 100Base-TX or 10Mbps and 100Mbps in both half-duplex and full-duplex modes. Additionally, the device provides an MDIO interface for PHY configuration. The EMAC supports MII and RMII interfaces. The rich peripheral set provides functions for controlling peripherals and communicating with external processors.

The device comes with a complete set of ARM9 and DSP development tools. This set of tools includes a C language compiler, a DSP assembly optimizer for simplifying the programming and scheduling process, and a Windows debugger interface for viewing source code execution.

• Dual-core SoC – 200MHz ARM926EJ-S RISC MPU – 200MHz C674x fixed- and floating-point VLIW DSP
• ARM926EJ-S core – 32-bit and 16-bit (Thumb) instructions – DSP instruction extensions – Single-cycle MAC – ARM Jazelle technology – Embedded ICE-RT for real-time debug
• ARM9 memory architecture – 16KB instruction cache – 16KB data cache – 8KB RAM (vector table) – 64KB ROM
• C674x instruction set features – Superset of C67x+ and C64x+ ISA – Up to 1600 MIPS and 1200 MFLOPS – Byte-addressable (8-bit, 16-bit, 32-bit, and 64-bit data) – 8-bit overflow protection – Bit-field extract, set, clear – Normalization, saturation, bit counting – Compact 16-bit instructions
• C674x two-level cache architecture – 32KB L1P program RAM/cache – 32KB L1D data RAM/cache – 256KB L2 unified mapped RAM/cache – Flexible RAM/cache partitioning (L1 and L2)
• EDMA3: – 2 channel controllers – 3 transfer controllers – 64 independent DMA channels – 16 quick DMA channels – Programmable transfer burst size
• TMS320C674x floating-point VLIW DSP core with load-store architecture supporting unaligned access – 64 general-purpose registers (32-bit) – 6 ALU (32-bit and 40-bit) functional units – Supports 32-bit integer, SP (IEEE single-precision/32-bit), and DP (IEEE double-precision/64-bit) floating-point – Up to 4 SP additions per clock, up to 4 DP additions per 2 clocks – Up to 2 floating-point (SP or DP) reciprocal approximation (RCPxP) and reciprocal square root approximation (RSQRxP) operations per cycle – 2 multiply functional units: – Mixed-precision IEEE floating-point multiply supporting up to: – 2 SP×SP→SP operations per clock – 2 SP×SP→DP operations per 2 clocks – 2 SP×DP→DP operations per 3 clocks – 2 DP×DP→DP operations per 4 clocks – Fixed-point multiply supporting 2×32×32-bit, 4×16×16-bit, or 8×8×8-bit multiplications per clock cycle, plus complex multiply support – Instruction compression for reduced code size – Conditional execution for all instructions – Hardware support for modulo loop operation – Protected mode operation – Additional support for error detection and program redirection
• Software support – TI DSP/BIOS – Chip support library and DSP library
• 128KB shared RAM
• 1.8V or 3.3V LVCMOS I/O (except USB and DDR2 interfaces)
• 2 external memory interfaces: – EMIFA – NOR (8-bit or 16-bit wide data) – NAND (8-bit or 16-bit wide data) – 16-bit SDRAM with 128MB address space – DDR2/mDDR memory controller with two options: – 16-bit DDR2 SDRAM with 256MB address space – 16-bit mDDR SDRAM with 256MB address space
• 3 configurable 16550-type UART modules: – With modem control signals – 16-byte FIFO – 16x or 13x oversampling options
• 2 SPI interfaces, each with multiple chip selects
• 2 MMC/SD card interfaces with SDIO support
• 2 master/slave I2C Bus
• PRUSS – 2 independent PRU cores – 32-bit load-store RISC architecture – 4KB instruction RAM per core – 512-byte data RAM per core – PRUSS can be disabled via software for power saving – In addition to the normal R31 output of the PRU core, register 30 of each PRU is exported from the subsystem – Standard power management mechanisms – Clock gating – Complete subsystem under a single PSC clock-gating domain – Dedicated interrupt controller – Dedicated switch fabric source
• USB 2.0 OTG port with integrated PHY (USB0) – USB 2.0 high-speed and full-speed device – USB 2.0 high-speed, full-speed, and low-speed host – Endpoint 0 (control) – Endpoints 1, 2, 3, and 4 (control, bulk, interrupt, or ISOC) RX and TX
• 1 McASP: – 2 clock zones and 16 serializer pins – Supports TDM, I2S, and similar formats – Supports DIT – FIFO buffers for transmit and receive
• 2 McBSP: – Supports TDM, I2S, and similar formats – AC97 audio codec interface – Telecom interface (ST-Bus, H100) – 128-channel TDM – FIFO buffers for transmit and receive
• 10/100Mbps Ethernet MAC (EMAC): – IEEE 802.3 compliant – MII – RMII – MDIO module
• RTC with 32kHz oscillator and dedicated power rail
• 3 × 64-bit general-purpose timers (each configurable as two 32-bit timers)
• 1 × 64-bit general-purpose timer or watchdog timer (configurable as two 32-bit timers)
• 2 eHRPWM modules: – Dedicated 16-bit time-base counter with period and frequency control – 6 single-edge outputs, 6 dual-edge symmetric outputs, or 3 dual-edge asymmetric outputs – Dead-band generation – PWM chopping via high-frequency carrier – Trip-zone input
• 3 × 32-bit eCAP modules: – Configurable as 3 capture inputs or 3 APWM outputs – Single-shot capture of up to 4 event timestamps
• Package: – 361-ball lead-free PBGA [ZWT suffix], 0.80mm ball pitch
• Commercial or extended temperature

• Professional/Private Mobile Radio (PMR)
• Industrial Automation
• Biometric Identification
• Smart Grid Substation Protection
• Industrial Portable Navigation Devices