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TI ADC09DJ1300AAVRoHS

Manufacturer
TI
MPN
ADC09DJ1300AAV
LCSC Part #
C5215308
Packaging
FCBGA-144(10x10)
Customer #
Key Attributes
Four-channel/Dual-channel/Single-channel 1.3 GSPS 9-bit Analog-to-Digital Converter (ADC) with JESD204C interface
Datasheetpdf iconTI ADC09DJ1300AAV
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QtyUnit PriceTotal Amount
1+$ 107.3811$ 107.38
30+$ 103.0503$ 3091.51
Standard Packaging168/Full Tray
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
ManufacturerTI
PackagingFCBGA-144(10x10)
Operating Temperature-40℃~+85℃
Clock/OscillatorBuilt-in
Clock Frequency1.3GHz
FeaturesMulti-chip synchronization;Synchronous triggering
Voltage ReferenceBuilt-in
InterfaceSerial port
Resolution(Bits)1.3GHz;9
S/N Ratio53.5dB
Voltage - Supply1.1V;1.9V
Number of Channels2
Integral non - linearity0.33LSB
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Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging168
Sales UnitPiece

Introduction

AI Translation

The ADC09xJ1300 is a series of 9-bit, 1.3GSPS four-channel/dual-channel/single-channel analog-to-digital converters (ADCs) with low power consumption, high sampling rate, and 9-bit resolution. They are well-suited for various multi-channel communication and test systems. The full-power input bandwidth (-3dB) of 6GHz also supports direct RF sampling in the L and S bands. It includes many clock functions to relax system hardware requirements, such as an internal phase-locked loop (PLL) with an integrated voltage-controlled oscillator (VCO) for generating the sampling clock. Four clock outputs are provided to time the logic and serializers/deserializers of FPGAs or ASICs. Timestamp inputs and outputs are provided for pulsed systems. The JESD204C serial interface reduces the system size by minimizing the amount of printed circuit board (PCB) wiring. The interface mode supports 2 to 8 channels (dual-channel and four-channel devices) or 1 to 4 channels (single-channel devices) and a serializer/deserializer baud rate of up to 17.16Gbps, enabling each application to achieve an optimal configuration.

Features

AI Translation
  • Resolution: 9-bit
  • Maximum sample rate: 1.3GSPS non-interleaved architecture
  • Internal dither reduces high-order harmonics
  • SNR (100MHz): 53.5dBFS
  • ENOB (100MHz): 8.5 bits
  • SFDR (100MHz): 64dBc
  • Noise floor (–20dBFS): -143dBFS
  • Full-scale input voltage: 800mVPP - DIFF
  • Full-power input bandwidth: 6GHz
  • Total supported SerDes lanes: 2 to 8 (quad/dual channel) or 1 to 4 (single channel)
  • Maximum baud rate: 17.16Gbps
  • 64B/66B and 8B/10B encoding modes
  • Subclass 1 deterministic latency, JESD204B receiver compatible
  • Optional internal sample clock generation
  • Four clock outputs for simplified system clocking
  • Reference clock for FPGA or adjacent ADC
  • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS):
    • Quad channel: 450mW per channel
    • Dual channel: 625mW per channel
    • Single channel: 940mW
  • Power supply: 1.1V/1.9V

Applications

AI Translation
  • LiDAR
  • Handheld test equipment
  • Multi-channel oscilloscopes and digitizers
  • Wireless communication test equipment
  • Optical Coherence Tomography (OCT)
  • SATCOM