HYNIX H5AG36EXNDX017N
| Manufacturer | |
| MPN | H5AG36EXNDX017N |
| LCSC Part # | C52145351 |
| Packaging | FBGA-96(13x7.5) |
| Customer # | |
| Key Attributes | FBGA-96(13x7.5) Memory (ICs) RoHS |
| Datasheet |  HYNIX H5AG36EXNDX017N |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | HYNIX | |
| Packaging | FBGA-96(13x7.5) |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 320 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
H5AG34EXNDX026N, H5AG38EXNDX026N, H5AG36EXNDX017N, H5AG38EXNJX026N, H5AG36EXNJX-017N is an 8Gb CMOS Double Data Rate IV (DDR4) Synchronous Dynamic Random Access Memory (SDRAM), ideally suited for main memory applications requiring high storage density and high bandwidth. The SK Hynix 8Gb DDR4 SDRAM provides fully synchronous operation, referenced to both the rising and falling edges of the clock. All address and control inputs are latched on the rising edge of CK (falling edge of CK#), while data, data strobes, and write data mask inputs are sampled on both their rising and falling edges. The data path employs internal pipelining and an 8-bit prefetch architecture to achieve extremely high bandwidth.
Features
- VDD = VDDQ = 1.2V ± 0.06V
- Fully differential clock input (CK, CK) operation
- Differential data strobe (DQS, DQS)
- On-chip DLL aligns DQ, DQS, and DQS transitions with CK transitions
- DM masks write data on both rising and falling edges of the data strobe
- All address and control inputs, except data, data strobe, and data mask, are latched on the rising edge of the clock
- Programmable burst length 4/8, supporting x4 sequential and interleave modes
- Burst length dynamically switchable
- 16 banks
- Average refresh interval (temperature range 0℃ ~ 95℃):
- 7.8µs at 0℃ ~ 85℃
- 3.9µs at 85℃ ~ 95℃
- JEDEC standard 78-ball FBGA (x4/x8), 96-ball FBGA (x16)
- Drive strength selectable via MRS
- Dynamic on-die termination support
- RTT_PARK and RTT_NOM termination states switchable via ODT pin
- Asynchronous reset pin support
- ZQ calibration support
- TDQS (Terminated Data Strobe) support (x8 only)
- Write leveling support
- 8-bit prefetch
- RoHS compliant
- Internal Vref DQ level generation
- Write CRC supported at all speed grades
- Maximum power saving mode support
- TCAR (Temperature Controlled Auto Refresh) mode support
- LP ASR (Low Power Auto Self-Refresh) mode support
- Fine granularity refresh support
- Per-DRAM addressability support
- Gear-down mode (1/2 rate, 1/4 rate) support
- Read/write programmable preamble support
- Self-refresh abort support
- CA parity (Command/Address parity) mode support
- Bank grouping implemented; CAS-to-CAS latency (tCCD_L, tCCD_S) available between banks accessed within same or different bank groups
- DBI (Data Bus Inversion) support (x8)
- MBIST PPR support
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 48.2874 | $ 48.29 |
| 30+ | $ 45.3722 | $ 1361.17 |
Standard Packaging320/Full Tray | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | HYNIX | |
| Packaging | FBGA-96(13x7.5) |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 320 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
H5AG34EXNDX026N, H5AG38EXNDX026N, H5AG36EXNDX017N, H5AG38EXNJX026N, H5AG36EXNJX-017N is an 8Gb CMOS Double Data Rate IV (DDR4) Synchronous Dynamic Random Access Memory (SDRAM), ideally suited for main memory applications requiring high storage density and high bandwidth. The SK Hynix 8Gb DDR4 SDRAM provides fully synchronous operation, referenced to both the rising and falling edges of the clock. All address and control inputs are latched on the rising edge of CK (falling edge of CK#), while data, data strobes, and write data mask inputs are sampled on both their rising and falling edges. The data path employs internal pipelining and an 8-bit prefetch architecture to achieve extremely high bandwidth.
Features
- VDD = VDDQ = 1.2V ± 0.06V
- Fully differential clock input (CK, CK) operation
- Differential data strobe (DQS, DQS)
- On-chip DLL aligns DQ, DQS, and DQS transitions with CK transitions
- DM masks write data on both rising and falling edges of the data strobe
- All address and control inputs, except data, data strobe, and data mask, are latched on the rising edge of the clock
- Programmable burst length 4/8, supporting x4 sequential and interleave modes
- Burst length dynamically switchable
- 16 banks
- Average refresh interval (temperature range 0℃ ~ 95℃):
- 7.8µs at 0℃ ~ 85℃
- 3.9µs at 85℃ ~ 95℃
- JEDEC standard 78-ball FBGA (x4/x8), 96-ball FBGA (x16)
- Drive strength selectable via MRS
- Dynamic on-die termination support
- RTT_PARK and RTT_NOM termination states switchable via ODT pin
- Asynchronous reset pin support
- ZQ calibration support
- TDQS (Terminated Data Strobe) support (x8 only)
- Write leveling support
- 8-bit prefetch
- RoHS compliant
- Internal Vref DQ level generation
- Write CRC supported at all speed grades
- Maximum power saving mode support
- TCAR (Temperature Controlled Auto Refresh) mode support
- LP ASR (Low Power Auto Self-Refresh) mode support
- Fine granularity refresh support
- Per-DRAM addressability support
- Gear-down mode (1/2 rate, 1/4 rate) support
- Read/write programmable preamble support
- Self-refresh abort support
- CA parity (Command/Address parity) mode support
- Bank grouping implemented; CAS-to-CAS latency (tCCD_L, tCCD_S) available between banks accessed within same or different bank groups
- DBI (Data Bus Inversion) support (x8)
- MBIST PPR support
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |