NXP MPC860TCZQ66D4

The MPC860 power quad integrated communications controller (PowerQUICC) is a versatile one-chip integrated microprocessor and peripheral combination designed for a variety of controller applications. It particularly excels in communications and networking systems. The MPC860 implements Power Architecture technology and contains a superset of Freescale’s MC68360 quad integrated communications controller (QUICC), referred to here as the QUICC, RISC communications proccessor module (CPM). The CPU on the MPC860 is a 32-bit core built on Power Architecture technology that incorporates memory management units (MMUs) and instruction and data caches. The CPM from the MC68360 QUICC has been enhanced by the addition of the inter-integrated controller (I²C) channel. The memory controller has been enhanced, enabling the MPC860 to support any type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket controller supports up to two sockets. A real-time clock has also been integrated.

• Embedded single-issue, 32-bit core (implementing the Power Architecture technology) with thirty-two 32-bit general-purpose registers (GPRs)
• The core performs branch prediction with conditional prefetch without conditional executio
• 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache
• 16-Kbyte instruction caches are four-way, set-associative with 256 sets; 4-Kbyte instructio caches are two-way, set-associative with 128 sets
• 8-Kbyte data caches are two-way, set-associative with 256 sets; 4-Kbyte data caches are two-way, set-associative with 128 sets
• Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks
• Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis
• MMUs with 32-entry TLB, fully-associative instruction, and data TLBs
• MMUs support multiple page sizes of 4-, 16-, and 512-Kbytes, and 8-Mbytes; 16 virtual address spaces and 16 protection groups
• Advanced on-chip-emulation debug mode
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Operates at up to 80 MHz
• Memory controller (eight banks)
• Contains complete dynamic RAM (DRAM) controller
• Each bank can be a chip select or the complement of RAS to support a DRAM bank
• Up to 15 wait states programmable per memory bank
• Glueless interface to DRAM, SIMMS, SRAM, EPROM, Flash EPROM, and other memory devices
• DRAM controller programmable to support most size and speed memory interfaces
• Four CAS lines, four complement of WE lines, and one complement of OE line
• Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
• Variable block sizes (32 Kbytes to 256 Mbytes)
• Selectable write protection
• On-chip bus arbitration logic
• General-purpose timers
• Four 16-bit timers or two 32-bit timers
• Gate mode can enable/disable counting
• Interrupt can be masked on reference match and event capture
• System integration unit (SIU)
• Bus monitor
• Software watchdog
• Periodic interrupt timer (PIT)
• Low-power stop mode
• Clock synthesizer
• Decrementer, time base, and real-time clock (RTC)
• Reset controller
• IEEE 1149.1 Std. test access port (JTAG)
• Interrupts
• Seven external interrupt request (IRQ) lines
• 12 port pins with interrupt capability
• 23 internal interrupt sources
• Programmable priority between SCCs
• Programmable highest priority request
• 10/100 Mbps Ethernet support, fully compliant with the IEEE 802.3u Standard (not available when using ATM over UTOPIA interface)
• ATM support compliant with ATM forum UNI 4.0 specification
• Cell processing up to 50–70 Mbps at 50-MHz system clock
• Cell multiplexing/demultiplexing
• Support of AAL5 and AAL0 protocols on a per-VC basis. AAL0 support enables OAM and software implementation of other protocols
• ATM pace control (APC) scheduler, providing direct support for constant bit rate (CBR) and unspecified bit rate (UBR) and providing control mechanisms enabling software support of available bit rate (ABR)
• Physical interface support for UTOPIA (10/100-Mbps is not supported with this interface) and byte-aligned serial (for example, T1/E1/ADSL)
• UTOPIA-mode ATM supports level-1 master with cell-level handshake, multi-PHY (up to four physical layer devices), connection to 25-, 51-, or 155-Mbps framers, and UTOPIA/system clock ratios of 1/2 or 1/3
• Serial-mode ATM connection supports transmission convergence (TC) function