- Pinout Diagram
- Footprint Diagram
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EDA ModelsEasyEDA
GigaDevice Semicon Beijing GDQ2BFAA-WQ
| Manufacturer | GigaDevice Semicon BeijingAsian Brands |
| MPN | GDQ2BFAA-WQ |
| LCSC Part # | C5184034 |
| Packaging | FBGA-96 |
| Customer # | |
| Key Attributes | 4Gbit 1.2V 1.333GHz DDR4 SDRAM FBGA-96 Memory (ICs) RoHS |
| Datasheet |  GigaDevice Semicon Beijing GDQ2BFAA-WQ |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | GigaDevice Semicon Beijing | |
| Packaging | FBGA-96 | |
| Refresh Current | 3.5mA | |
| Memory Size | 4Gbit | |
| Voltage - Supply | 1.2V | |
| Operating temperature | -40℃~+95℃ | |
| Clock Frequency | 1.333GHz | |
| Features | Auto self-refresh;Data mask function;Dynamic on-chip termination;Asynchronous reset function;CRC function;Auto precharge function;ZQ calibration function | |
| Memory Format | DDR4 SDRAM | |
| Current - Supply | 64mA |
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Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 128 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Power Supply: VDD = VDDQ = 1.2V (1.14V ~ 1.26V); VPP = 2.5V (2.375V ~ 2.75V)
- JEDEC Standard Package: 96-Ball FBGA (x16)
- Array Configuration: 8 Banks (x16), divided into 2 groups of 4 Banks each
- 8n-bit prefetch architecture
- Burst Length: BL8 and BC4 (with burst chop) supported
- Programmable CAS Latency
- Programmable CAS Write Latency
- Internally generated VREF for data input
- Data Mask supported for write data
- On-Die Termination: Nominal, Park, and Dynamic ODT supported
- Interface: 1.2V pseudo open-drain I/O
- Differential clock and data strobe inputs
- Per-DRAM addressability supported
- Data Bus Inversion (DBI) supported
- Asynchronous power-on reset supported
- Maximum power-saving mode supported
- Precharge: Auto-precharge option per burst access supported
- Operating Case Temperature: -40°C ≤ TCASE ≤ 95°C
- Auto Refresh and Self Refresh modes supported
- Average Refresh Interval: 7.8μs for -40°C ≤ TCASE ≤ 85°C; 3.9μs for 85°C < TCASE ≤ 95°C
- 2x and 4x Fine Granularity Refresh modes supported for reduced tRFC
- Programmable data strobe preamble supported
- Command/Address parity supported
- Write CRC supported
- Connectivity Test Mode supported
- Gear-Down Mode supported
- Output driver calibration via ZQ pin
- Compliant with JEDEC JESD-79-4D
- RoHS compliant
In-Stock: 978
978 In stock, ships now
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| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 21.9457 | $ 21.95 |
| 30+ | $ 20.8157 | $ 624.47 |
Standard Packaging128/Full Tray | ||
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Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory (ICs) | |
| Manufacturer | GigaDevice Semicon Beijing | |
| Packaging | FBGA-96 | |
| Refresh Current | 3.5mA | |
| Memory Size | 4Gbit | |
| Voltage - Supply | 1.2V | |
| Operating temperature | -40℃~+95℃ | |
| Clock Frequency | 1.333GHz | |
| Features | Auto self-refresh;Data mask function;Dynamic on-chip termination;Asynchronous reset function;CRC function;Auto precharge function;ZQ calibration function | |
| Memory Format | DDR4 SDRAM | |
| Current - Supply | 64mA |
Report an ErrorShow similar products (0) >
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 128 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Features
AI Translation
- Power Supply: VDD = VDDQ = 1.2V (1.14V ~ 1.26V); VPP = 2.5V (2.375V ~ 2.75V)
- JEDEC Standard Package: 96-Ball FBGA (x16)
- Array Configuration: 8 Banks (x16), divided into 2 groups of 4 Banks each
- 8n-bit prefetch architecture
- Burst Length: BL8 and BC4 (with burst chop) supported
- Programmable CAS Latency
- Programmable CAS Write Latency
- Internally generated VREF for data input
- Data Mask supported for write data
- On-Die Termination: Nominal, Park, and Dynamic ODT supported
- Interface: 1.2V pseudo open-drain I/O
- Differential clock and data strobe inputs
- Per-DRAM addressability supported
- Data Bus Inversion (DBI) supported
- Asynchronous power-on reset supported
- Maximum power-saving mode supported
- Precharge: Auto-precharge option per burst access supported
- Operating Case Temperature: -40°C ≤ TCASE ≤ 95°C
- Auto Refresh and Self Refresh modes supported
- Average Refresh Interval: 7.8μs for -40°C ≤ TCASE ≤ 85°C; 3.9μs for 85°C < TCASE ≤ 95°C
- 2x and 4x Fine Granularity Refresh modes supported for reduced tRFC
- Programmable data strobe preamble supported
- Command/Address parity supported
- Write CRC supported
- Connectivity Test Mode supported
- Gear-Down Mode supported
- Output driver calibration via ZQ pin
- Compliant with JEDEC JESD-79-4D
- RoHS compliant
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |