Infineon S27KL0642DPBHB023

Infineon® 64Mb HYPERRAM™ device is a high-speed CMOS self-refresh DRAM with a HYPERBURST™ interface. Its DRAM array uses dynamic memory cells that require periodic refresh. When the memory is not being actively read or written by the HYPERBUS™ interface master controller (host), the on-device refresh control logic manages the refresh operations of the DRAM array. Since the host does not need to manage any refresh operations, the DRAM array behaves to the host like a memory that uses static storage cells and retains data without requiring refresh. Therefore, this memory is more accurately described as pseudo-static RAM (PSRAM). Since DRAM cells cannot be refreshed during read or write transactions, the host is required to limit the length of read or write burst transfers to allow the internal logic to perform refresh operations when needed. The host must limit the duration of transactions and allow increased initial access latency at the start of a new transaction when the memory indicates that a refresh operation is required. HYPERBUS™ is a low signal count, DDR interface that enables high-speed read and write throughput. The DDR protocol transfers two bytes of data per clock cycle on the DQ[7:0] input/output signals. A read or write transaction on HYPERBUS™ consists of a series of 16-bit wide, one-clock-cycle data transfers across the internal HYPERRAM™ array, and two corresponding 8-bit wide, half-clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. The device provides 1.8V VCC/VCCQ or 3.0V VCC/VCCQ (nominal) for array (VCC) and I/O buffer (VCCQ) supplies, differentiated through different ordering part numbers (OPNs). Command, address, and data information are transferred via eight HYPERBUS™ DQ[7:0] signals. The clock (CK#, CK) is used by the HYPERBUS™ slave device for information capture when receiving commands, addresses, or data on the DQ signals. Command or address values are center-aligned to clock transitions. Each transaction begins with the assertion of CS# and the command-address (CA) signal, followed by clock transitions to transfer data.

• HYPERBUSTM Interface
• 1.8 V / 3.0 V Interface Support
• Single-ended Clock (CK) - 11 Bus Signals
• Optional Differential Clock (CK, CK#) - 12 Bus Signals
• Chip Select (CS#)
• 8-bit Data Bus (DQ[7:0])
• Hardware Reset (RESET#)
• Bidirectional Read/Write Data Strobe (RWDS)
• Output at the beginning of all transactions to indicate refresh latency
• Output as read data strobe during read transactions
• Input as write data mask during write transactions
• Optional DDR Center-Aligned Read Strobe (DCARS)
• During read transactions, RWDS is shifted by a second clock with a phase difference from CK
• This phase-shifted clock is used to move RWDS transition edges into the read data eye
• Maximum Clock Rate 200 MHz
• DDR
• Data transferred on both edges of the clock
• Data throughput up to 400 MBps (3,200 Mbps)
• Configurable burst features
• Linear Burst
• Wrap Burst Length
• 16 Bytes (8 Clocks)
• 32 Bytes (16 Clocks)
• 64 Bytes (32 Clocks)
• 128 Bytes (64 Clocks)
• Hybrid Option
• One wrap burst followed by linear burst
• Configurable output drive strength
• Hybrid Sleep Mode
• Deep Power-Down Mode
• Partial Memory Array (1/8, 1/4, 1/2, etc.)
• Full Refresh
• 24-ball FBGA Package
• Industrial (I): -40°C to +85°C
• Industrial Plus (V): -40°C to +105°C
• Automotive, AEC-Q100 Grade 3: -40°C to +85°C
• Automotive, AEC-Q100 Grade 2: -40°C to +105°C
• 38 nm DRAM Technology