JSMSEMI 74HC595D

The 74HC595D is an 8-bit serial-in, serial-or-parallel-out shift register with a storage register and 3-state outputs. The shift register and storage register have independent clocks. The device features a serial input (DS) and a serial output (Q7S) for cascading, along with an asynchronous reset MR input. A low level on MR resets the shift register. Data is shifted on the rising edge of the SHCP input. Data in the shift register is transferred to the storage register on the rising edge of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Whenever the output enable input (OE) is low, the data in the storage register appears at the outputs. A high level on OE causes the outputs to assume a high-impedance state. Changes on the OE input do not affect the state of the registers. Inputs are equipped with clamp diodes, allowing input interfaces to be connected to voltages exceeding VCC using current-limiting resistors.

• Input level: CMOS
• 8-bit serial input
• 8-bit serial/parallel output
• Storage register with tri-state output
• Shift register with direct clear
• 100MHz (typical) shift-out frequency
• Operating temperature range: -40°C ~ +105°C
• Shift register counter
• Sequential pulse generator
• Serial-to-parallel data conversion
• LED drive