ADI ADSP-21489KSWZ-4B

High-performance 32/40-bit floating-point processor optimized for high-performance audio processing Single Instruction, Multiple Data (SIMD) computational architecture On-chip memory: 5 Mb on-chip RAM, 4 Mb on-chip ROM Operating frequency up to 400 MHz Source code compatible with all other products in the SHARC family Audio-centric peripherals including: Digital Application Interface, serial ports, precision clock generator, S/PDIF transceiver, asynchronous sample rate converter, input data port, and more

The ADSP-2148x SHARC processor belongs to the SIMD SHARC family of DSPs, based on Super Harvard Architecture. This processor family is source code compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x, ADSP-2116x DSPs, as well as the first-generation ADSP-2106x SHARC processor operating in SISD (Single Instruction, Single Data) mode. It features large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Application Interface (DAI).

This processor family employs two computational units, delivering significantly improved performance for various DSP algorithms compared to previous SHARC processors. Running at 400 MHz with SIMD computational hardware, this processor family is capable of executing 2.4 GFLOPS.

• Two processing elements (PEx, PEy), each consisting of an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses supporting 2×64-bit data transfers per core processor cycle between memory and the core
• A periodic interval timer with pin assignments
• On-chip SRAM (5 Mb) and mask-programmable ROM (4 Mb)
• JTAG test access port for emulation and boundary scan. JTAG provides software debug capability via user breakpoints with flexible exception handling support
• IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers
• Peripheral and external port buses for core connectivity
• External port with AMI and SDRAM controllers
• 4 PWM control units
• 1 memory-to-memory (MTM) unit for internal-to-internal memory transfers
• Digital application interface, including 4 precision clock generators (PCG), 1 input data port (IDP/PDAP) for serial and parallel interconnect, 1 S/PDIF receiver/transmitter, 4 asynchronous sample rate converters, 8 serial ports, and 1 flexible signal routing unit (DAI SRU)
• Digital peripheral interface, including 2 timers, 1 two-wire interface (TWI), 1 UART, 2 SPI, 2 PCG, 1 PWM unit, and 1 flexible signal routing unit (DPI SRU2)
• Each PE contains a set of compute units consisting of an ALU, multiplier, and shifter, executing all operations in a single cycle and arranged in parallel to maximize computational throughput
• A single multifunction instruction executes parallel ALU and multiplier operations; in SIMD mode, parallel ALU and multiplier operations execute simultaneously in both PEs
• Compute units support IEEE 32-bit single-precision floating-point, 40-bit extended-precision floating-point, and 32-bit fixed-point data formats
• The processor contains a core timer for generating periodic software interrupts, configurable to use FLAG3 as the timer expiration signal
• Each PE contains a general-purpose data register file for transferring data between compute units and data buses, and for storing intermediate results
• Many processor registers have shadow registers that can be activated during interrupt handling for fast context switching
• USTAT (4) registers enable easy bit manipulation (set, clear, toggle, test, XOR) on all peripheral registers (control/status)
• The data bus exchange register (PX) allows data transfer between the 64-bit PM data bus and the 64-bit DM data bus, or between the 40-bit register file and the PM/DM data buses
• The ADSP-2148x employs an enhanced Harvard architecture, using separate program and data memory buses along with an on-chip instruction cache to simultaneously fetch 4 operands (2 per data bus) and 1 instruction per cycle
• The processor contains an on-chip instruction cache supporting three-bus operation to fetch one instruction and four data values, enabling full-speed execution of core loop operations
• Two DAGs support indirect addressing and hardware implementation of circular data buffers, containing sufficient registers to create up to 32 circular buffers with automatic address pointer wrap-around handling
• 48-bit instruction words support a wide range of parallel operations for concise programming
• In addition to standard 48-bit instructions inherited from previous-generation SHARC processors, new 16-bit and 32-bit instructions are supported — a feature known as Variable Instruction Set Architecture (VISA)
• The program sequencer supports fetching these 16-bit and 32-bit instructions from internal and external SDRAM memory
• The processor's SRAM is configurable as up to 160K words of 32-bit data, 320K words of 16-bit data, 106.7K words of 48-bit instructions (or 40-bit data), or a combination of different word sizes, provided the total does not exceed 5 Mb
• All memory is accessible via 16-bit, 32-bit, 48-bit, or 64-bit words, with 16-bit floating-point storage format support, doubling the amount of data that can be stored on-chip
• Conversion between 32-bit and 16-bit floating-point is performed with a single instruction
• Using the DM and PM buses — each dedicated to one memory block — single-cycle execution of two simultaneous data transfers is guaranteed