ADI AD6643BCPZ-250

The AD6643 is an 11-bit, 200 MSPS/250 MSPS, dual-channel IF receiver designed specifically to support multi-antenna systems in telecommunications applications requiring high dynamic range performance, low power consumption, and small form factor. The device includes two high-performance ADCs and a noise shaping requantizer (NSR) digital block. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic; the first stage of each ADC differential pipeline incorporates a wide-bandwidth switched-capacitor sampling network. An integrated voltage reference simplifies design. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, maintaining excellent converter performance. The output of each ADC is internally connected to the NSR block. The integrated NSR circuit improves SNR performance over a narrower frequency band within the Nyquist bandwidth. The device supports two different output modes, selectable via SPI. When the NSR feature is enabled, the AD6643 processes the ADC output to achieve higher SNR performance within a limited portion of the Nyquist bandwidth while maintaining 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sampling clock. For example, at a sampling clock rate of 185 MSPS, in 22% mode the AD6643 achieves up to 75.5 dBFS SNR over a 40 MHz bandwidth; in 33% mode, it achieves up to 73.7 dBFS SNR over a 60 MHz bandwidth. When the NSR block is disabled, ADC data is delivered directly to the output at 11-bit resolution. In this operating mode, the AD6643 achieves up to 66.5 dBFS SNR across the full Nyquist bandwidth. Consequently, the AD6643 is well suited for telecommunications applications such as digital predistortion observation paths requiring wider bandwidth. After digital signal processing, the multiplexed output data is routed to two 11-bit output ports at a maximum data rate of 400 Mbps (DDR). These outputs are configured as LVDS, supporting ANSI-644 levels. The AD6643 receiver is capable of digitizing a wide IF spectrum. Each receiver is designed for synchronous reception from different antennas. This IF sampling architecture significantly reduces device cost and complexity compared to conventional analog techniques or lower-integration digital approaches. Flexible power-down options provide significant power savings. Device configuration and control programming is accomplished via a 3-wire SPI-compatible serial interface, which offers multiple operating modes to support board-level system testing. The AD6643 is housed in a 64-lead, lead-free, 9 mm × 9 mm footprint chip-scale package (LFCSP_VQ), RoHS compliant, rated for the −40°C to +85°C industrial temperature range.

• 11-bit, 250 MSPS output data rate per channel
• Performance with NSR enabled — SNR: 74.5 dBFS (55 MHz band, 90 MHz, 250 MSPS); SNR: 72.0 dBFS (82 MHz band, 90 MHz, 250 MSPS)
• Performance with NSR disabled — SNR: 66.2 dBFS (90 MHz, 250 MSPS); SFDR: 85 dBc (185 MHz, 250 MSPS)
• Total power consumption: 706 mW (200 MSPS)
• 1.8 V supply voltage
• LVDS (ANSI-644 levels) outputs
• 1-to-8 integer input clock divider (maximum input frequency 625 MHz)
• On-chip ADC voltage reference
• Flexible analog input range: 1.4 V p-p to 2.0 V p-p (nominal 1.75 V p-p)
• Differential analog input, 400 MHz bandwidth
• 95 dB channel isolation/crosstalk
• Serial port control
• Power-saving power-down mode
• Compact, space-saving 9 mm × 9 mm × 0.85 mm, 64-lead LFCSP integrating two ADCs
• Pin-selectable noise shaping requantizer (NSR) improves SNR when bandwidth is reduced to a maximum of 60 MHz at 185 MSPS
• LVDS digital output interface configured for low-cost FPGA families
• Single 1.8 V supply operation
• Standard SPI supports various product features and functions, including: data formatting (offset binary or two's complement), NSR, power-down, test modes, and reference mode
• On-chip 1-to-8 integer input clock divider and multichip synchronization support a wide range of clocking schemes and multichannel subsystems

• Communications
• Diversity radio and smart antenna (MIMO) systems
• Multi-mode digital receivers (3G) WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
• I/Q demodulation systems
• General-purpose software-defined radio